A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology

Wei-Zen Chen; Tai You Lu; Yan Ting Wang; Jhong Ting Jian; Yi Hung Yang; Guo Wei Huang; Wen De Liu; Chih Hua Hsiao; Shu Yu Lin; Jung Yen Liao

doi:10.1109/VLSIC.2012.6243765

A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology

Wei-Zen Chen^*, Tai You Lu, Yan Ting Wang, Jhong Ting Jian, Yi Hung Yang, Guo Wei Huang, Wen De Liu, Chih Hua Hsiao, Shu Yu Lin, Jung Yen Liao

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3 ^rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm ². This chip drains 24mW from a 1.2V power supply.

原文	English
主出版物標題	2012 Symposium on VLSI Circuits, VLSIC 2012
頁面	12-13
頁數	2
DOIs	https://doi.org/10.1109/VLSIC.2012.6243765
出版狀態	Published - 28 9月 2012
事件	2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States 持續時間: 13 6月 2012 → 15 6月 2012

出版系列

名字	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2012 Symposium on VLSI Circuits, VLSIC 2012
國家/地區	United States
城市	Honolulu, HI
期間	13/06/12 → 15/06/12

存取文件

10.1109/VLSIC.2012.6243765

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Link to publication in Scopus

引用此

Chen, W.-Z., Lu, T. Y., Wang, Y. T., Jian, J. T., Yang, Y. H., Huang, G. W., Liu, W. D., Hsiao, C. H., Lin, S. Y., & Liao, J. Y. (2012). A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology. 於 2012 Symposium on VLSI Circuits, VLSIC 2012 (頁 12-13). 文章 6243765 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2012.6243765

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title = "A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology",

abstract = "A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3 rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm 2. This chip drains 24mW from a 1.2V power supply.",

keywords = "Mixer, PLL, RSSI, THz",

author = "Wei-Zen Chen and Lu, {Tai You} and Wang, {Yan Ting} and Jian, {Jhong Ting} and Yang, {Yi Hung} and Huang, {Guo Wei} and Liu, {Wen De} and Hsiao, {Chih Hua} and Lin, {Shu Yu} and Liao, {Jung Yen}",

year = "2012",

month = sep,

day = "28",

doi = "10.1109/VLSIC.2012.6243765",

language = "English",

isbn = "9781467308458",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

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note = "2012 Symposium on VLSI Circuits, VLSIC 2012 ; Conference date: 13-06-2012 Through 15-06-2012",

}

Chen, W-Z, Lu, TY, Wang, YT, Jian, JT, Yang, YH, Huang, GW, Liu, WD, Hsiao, CH, Lin, SY & Liao, JY 2012, A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology. 於 2012 Symposium on VLSI Circuits, VLSIC 2012., 6243765, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 頁 12-13, 2012 Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, United States, 13/06/12. https://doi.org/10.1109/VLSIC.2012.6243765

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AU - Chen, Wei-Zen

AU - Lu, Tai You

AU - Wang, Yan Ting

AU - Jian, Jhong Ting

AU - Yang, Yi Hung

AU - Huang, Guo Wei

AU - Liu, Wen De

AU - Hsiao, Chih Hua

AU - Lin, Shu Yu

AU - Liao, Jung Yen

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N2 - A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3 rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm 2. This chip drains 24mW from a 1.2V power supply.

AB - A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3 rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm 2. This chip drains 24mW from a 1.2V power supply.

KW - Mixer

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KW - RSSI

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DO - 10.1109/VLSIC.2012.6243765

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SN - 9781467308458

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

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BT - 2012 Symposium on VLSI Circuits, VLSIC 2012

T2 - 2012 Symposium on VLSI Circuits, VLSIC 2012

Y2 - 13 June 2012 through 15 June 2012

ER -

A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology

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