A 160-GHz frequency-translation PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating a frequency tripler for frequency down conversion. A transformer-based VCO is utilized to alleviate capacitive and resistive load associated with varactor and succeeding buffer stages. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatic frequency sweeping and fast locking. Fabricated in 65 nm CMOS technology, the chip size is 0.92 mm2. The PLL locking time is less than 3 μ s. This chip drains 24 mW from a 1.2 V power supply.
|頁（從 - 到）||1648-1655|
|期刊||IEEE Transactions on Circuits and Systems I: Regular Papers|
|出版狀態||Published - 1 1月 2014|