A 14 μJ/Decision Keyword Spotting Accelerator With In-SRAM-Computing and On Chip Learning for Customization

Yu Hsiang Chiang, Tian-Sheuan Chang, Shyh Jye Jou

研究成果: Article同行評審

摘要

Keyword spotting (KWS) has gained popularity as a natural way to interact with consumer devices in recent years. However, because of its always on nature and the variety of speech, it necessitates a low-power design as well as user customization. This article describes a low-power, energy-efficient KWS accelerator with static random access memory (SRAM)-based in-memory computing (IMC) and on-chip learning for user customization. However, IMC is constrained by macro size, limited precision, and nonideal effects. To address the issues mentioned above, this article proposes bias compensation and fine-tuning using an IMC-aware model design. Furthermore, because learning with low-precision edge devices results in zero error and gradient values due to quantization, this article proposes error scaling and small gradient accumulation to achieve the same accuracy as ideal model training. The simulation results show that with user customization, we can recover the accuracy loss from 51.08% to 89.76% with compensation and fine-tuning and further improve to 96.71% with customization. The chip implementation can successfully run the model with only 14 μJ per decision. When compared to the state-of-the-art works, the presented design has higher energy efficiency with additional on-chip model customization capabilities for higher accuracy.

原文English
頁(從 - 到)1-9
頁數9
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DOIs
出版狀態Accepted/In press - 2022

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