TY - GEN
T1 - A 135mW fully integrated data processor for next-generation sequencing
AU - Wu, Yi Chung
AU - Hung, Jui-Hung
AU - Yang, Chia Hsiang
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/3/2
Y1 - 2017/3/2
N2 - DNA sequencing is the process of determining the precise order of nucleotides (A, C, G, T) within a DNA molecule and is now indispensable for genetics and medical research. Next-generation sequencing (NGS), in which short DNA fragments can be sequenced in a massively parallel fashion, enables high-throughput sequencing [1]. However, the succeeding data analysis, also known as DNA mapping, is excessively time consuming. DNA mapping can be partitioned into Suffix Array (SA) Sorting and Backward Searching. Dedicated hardware designs have been proposed to enhance the speed, but only for the less complex Backward Searching [2]. Feasible hardware for the most complicated part, SA sorting, has never been explored. This work presents a fully integrated NGS data processor that realizes both SA sorting and Backward Searching. The distributed sort algorithm is utilized to reduce the sorting complexity. The throughput of SA sorting is maximized through 2,048 insertion-sorting elements. Dedicated overflow and splitter caches are embedded to reduce the computation latency. With the optimized hardware architecture, the NGS processor achieves orders of magnitude improvement in both energy and throughput metrics compared to the high-end generic processors.
AB - DNA sequencing is the process of determining the precise order of nucleotides (A, C, G, T) within a DNA molecule and is now indispensable for genetics and medical research. Next-generation sequencing (NGS), in which short DNA fragments can be sequenced in a massively parallel fashion, enables high-throughput sequencing [1]. However, the succeeding data analysis, also known as DNA mapping, is excessively time consuming. DNA mapping can be partitioned into Suffix Array (SA) Sorting and Backward Searching. Dedicated hardware designs have been proposed to enhance the speed, but only for the less complex Backward Searching [2]. Feasible hardware for the most complicated part, SA sorting, has never been explored. This work presents a fully integrated NGS data processor that realizes both SA sorting and Backward Searching. The distributed sort algorithm is utilized to reduce the sorting complexity. The throughput of SA sorting is maximized through 2,048 insertion-sorting elements. Dedicated overflow and splitter caches are embedded to reduce the computation latency. With the optimized hardware architecture, the NGS processor achieves orders of magnitude improvement in both energy and throughput metrics compared to the high-end generic processors.
UR - http://www.scopus.com/inward/record.url?scp=85016242771&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2017.7870356
DO - 10.1109/ISSCC.2017.7870356
M3 - Conference contribution
AN - SCOPUS:85016242771
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 252
EP - 253
BT - 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
A2 - Fujino, Laura C.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 64th IEEE International Solid-State Circuits Conference, ISSCC 2017
Y2 - 5 February 2017 through 9 February 2017
ER -