A 135mW fully integrated data processor for next-generation sequencing

Yi Chung Wu, Jui-Hung Hung, Chia Hsiang Yang

研究成果: Conference contribution同行評審

10 引文 斯高帕斯(Scopus)

摘要

DNA sequencing is the process of determining the precise order of nucleotides (A, C, G, T) within a DNA molecule and is now indispensable for genetics and medical research. Next-generation sequencing (NGS), in which short DNA fragments can be sequenced in a massively parallel fashion, enables high-throughput sequencing [1]. However, the succeeding data analysis, also known as DNA mapping, is excessively time consuming. DNA mapping can be partitioned into Suffix Array (SA) Sorting and Backward Searching. Dedicated hardware designs have been proposed to enhance the speed, but only for the less complex Backward Searching [2]. Feasible hardware for the most complicated part, SA sorting, has never been explored. This work presents a fully integrated NGS data processor that realizes both SA sorting and Backward Searching. The distributed sort algorithm is utilized to reduce the sorting complexity. The throughput of SA sorting is maximized through 2,048 insertion-sorting elements. Dedicated overflow and splitter caches are embedded to reduce the computation latency. With the optimized hardware architecture, the NGS processor achieves orders of magnitude improvement in both energy and throughput metrics compared to the high-end generic processors.

原文English
主出版物標題2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
編輯Laura C. Fujino
發行者Institute of Electrical and Electronics Engineers Inc.
頁面252-253
頁數2
ISBN(電子)9781509037575
DOIs
出版狀態Published - 2 3月 2017
事件64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States
持續時間: 5 2月 20179 2月 2017

出版系列

名字Digest of Technical Papers - IEEE International Solid-State Circuits Conference
60
ISSN(列印)0193-6530

Conference

Conference64th IEEE International Solid-State Circuits Conference, ISSCC 2017
國家/地區United States
城市San Francisco
期間5/02/179/02/17

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