A 135-mW Fully Integrated Data Processor for Next-Generation Sequencing

Yi Chung Wu, Chia Hua Chang, Jui-Hung Hung*, Chia Hsiang Yang

*此作品的通信作者

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

Next-generation sequencing (NGS) enables high-throughput sequencing, in which short DNA fragments can be sequenced in a massively parallel fashion. However, the essential algorithm behind the succeeding NGS data analysis, DNA mapping, is still excessively time consuming. DNA mapping can be partitioned into two parts: suffix array (SA) sorting and backward searching. Dedicated hardware designs for the less-complex backward searching have been proposed, but feasible hardware for the most complicated part, SA sorting, has never been explored. Based on the memory-efficient sBWT algorithm, this work is the first integrated NGS data processor for the entire DNA mapping. The κ-ordered Ferragina and Manzini index used in the sBWT algorithm is leveraged to improve storage capacity and reduce hardware complexity. The proposed NGS data processor realizes the sBWT algorithm through bucket sorting, suffix grouping, and suffix sorting circuits. Key design parameters are analyzed to achieve the optimal performance with respect to hardware cost and execution time. Fabricated in 40-nm CMOS, the NGS data processor dissipates 135 mW at 200 MHz from a 0.9-V supply. With 1-GB external memory, the chip can analyze human DNA within 10 min. This work achieves 43 065 × and 8 971 × [3208 × and 402× ] higher energy efficiency (throughput-to-area ratio) than the high-end CPU and GPU solutions, respectively.

原文English
文章編號8094922
頁(從 - 到)1216-1225
頁數10
期刊IEEE Transactions on Biomedical Circuits and Systems
11
發行號6
DOIs
出版狀態Published - 1 十二月 2017

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