A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications

Xin Ru Lee*, Chih Wen Yang, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

In this paper, an over Gb/s stochastic nonbinary LDPC (NB-LDPC) decoder chip is first-reported. The operation of proposed decoder is transformed to logarithm domain, so that the decoding complexity is mitigated by the simpler summations and fewer bit-width. In addition, the storage requirements are dramatically reduced by truncated TFM architecture. After, benefited from architecture optimizations and symbol-serial property, the routing capability of proposed decoder is extraordinarily enhanced. According to the measurement results, this decoder can deliver 1.31Gb/s throughput under 368MHz clock frequency with the corresponding energy-efficiency of 0.45nJ/bit. Compared to other NB-LDPC decoders, our stochastic NB-LDPC decoder with 96.6% chip utilization improves 2x area-efficiency and 7x energy-efficiency.

原文English
主出版物標題ESSCIRC 2015 - Proceedings of the 41st European Solid-State Circuits Conference
編輯Franz Dielacher, Wolfgang Pribyl, Gernot Hueber
發行者IEEE Computer Society
頁面96-99
頁數4
ISBN(電子)9781467374705
DOIs
出版狀態Published - 14 9月 2015
事件41st European Solid-State Circuits Conference, ESSCIRC 2015 - Graz, Austria
持續時間: 14 9月 201518 9月 2015

出版系列

名字European Solid-State Circuits Conference
2015-October
ISSN(列印)1930-8833

Conference

Conference41st European Solid-State Circuits Conference, ESSCIRC 2015
國家/地區Austria
城市Graz
期間14/09/1518/09/15

指紋

深入研究「A 1.31Gb/s, 96.6% utilization stochastic nonbinary LDPC decoder for small cell applications」主題。共同形成了獨特的指紋。

引用此