A 13 × W, 94 mK Resolution, CMOS PD ΔΣ M Temperature-to-Digital Converter With Power-Gating Technique

Ying Jie Huang*, Yu Chiao Huang, Yu Hao Chiu, Wen Pin Tsai, Yu Te Liao

*此作品的通信作者

研究成果: Conference contribution同行評審

摘要

This paper presents a CMOS phase-domain delta-sigma modulator ( P D Δ Σ M) that digitizes temperaturedependent phase shifts resulting from driving a poly-phase filter (PPF) at a constant frequency. Closed-loop architecture with a power-gating technique is applied to improve linearity and power efficiency. The design is implemented in a 0.18 μ m CMOS process. The temperature sensor has an inaccuracy of ± 2.2°C(3σ) from -40°C to 85° C. Furthermore, the design achieves a resolution of 94 mK at 1 k S a/ s, while the chip area is 0.19 m m2. The power consumption is 13 μ W, resulting in an inaccuracy FoM of 161.1 n J%2.

原文English
主出版物標題ESSCIRC 2023 - IEEE 49th European Solid State Circuits Conference
發行者IEEE Computer Society
頁面17-20
頁數4
ISBN(電子)9798350304206
DOIs
出版狀態Published - 2023
事件49th IEEE European Solid State Circuits Conference, ESSCIRC 2023 - Lisbon, Portugal
持續時間: 11 9月 202314 9月 2023

出版系列

名字European Solid-State Circuits Conference
2023-September
ISSN(列印)1930-8833

Conference

Conference49th IEEE European Solid State Circuits Conference, ESSCIRC 2023
國家/地區Portugal
城市Lisbon
期間11/09/2314/09/23

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