A 1.2V interference-sturdiness, dc-offset calibrated cmos receiver utilizing a current-mode filter for uwb

Horng Yuan Shih, Wei Hsien Chen, Kai Chenug Juang, Tzu Yi Yang, Chien-Nan Kuo

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

An interference-sturdiness receiver with a current-mode filter for 3-5GHz UWB applications is implemented in a 1.2V 0.13(im CMOS process. The chip provides a maximum voltage gain of 70dB and a dynamic range of 60dB. The measured in-band OIP3 is +9.39dBm, out-of-band IIP3 -15dBm and noise figure 6.8dB in the maximum gain mode. An algorithm for the automatic digital DC offset calibration is also demonstrated.

原文English
主出版物標題Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
頁面345-348
頁數4
DOIs
出版狀態Published - 1 十二月 2008
事件2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
持續時間: 3 十一月 20085 十一月 2008

出版系列

名字Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

Conference

Conference2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
國家/地區Japan
城市Fukuoka
期間3/11/085/11/08

指紋

深入研究「A 1.2V interference-sturdiness, dc-offset calibrated cmos receiver utilizing a current-mode filter for uwb」主題。共同形成了獨特的指紋。

引用此