摘要
This work presents a 12b 100MS/s zero-crossing-based switched-capacitor CMOS pipelined analog-to-digital converter (ADC). The proposed ADC improves the resolution, power efficiency, and sample rate of the fully differential zero-crossing-based circuits and features a 90nm CMOS technology. Offset tolerance, current splitting, and a digital correction scheme were implemented to correct mismatches among current sources. Post-layout simulations show that the SNDR is 72.6dB when the input is close to the Nyquist rate. The power consumption is 20.8mW from a 1.2V supply and the figure-of-merit (FOM) is 59.6 fJ/conversion. The chip area occupies 2.88mm 2.
原文 | English |
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頁(從 - 到) | 77-83 |
頁數 | 7 |
期刊 | International Journal of Electrical Engineering |
卷 | 19 |
發行號 | 2 |
出版狀態 | Published - 4月 2012 |