A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression

Ming Chiuan Su; Wei-Zen Chen; Pei Si Wu; Yu Hsian Chen; Chao Cheng Lee; Shyh-Jye Jou

doi:10.1109/CICC.2013.6658469

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression

Ming Chiuan Su, Wei-Zen Chen, Pei Si Wu, Yu Hsian Chen, Chao Cheng Lee, Shyh-Jye Jou

電子研究所

研究成果: Conference contribution › 同行評審

3 引文斯高帕斯（Scopus）

摘要

A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UI_pp input data jitter, the recovered clock jitter at 2GHz is 2.94ps_rms. The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200×150μm².

原文	English
主出版物標題	Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（列印）	9781467361460
DOIs	https://doi.org/10.1109/CICC.2013.6658469
出版狀態	Published - 7 11月 2013
事件	35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, 美國持續時間: 22 9月 2013 → 25 9月 2013

出版系列

名字	Proceedings of the Custom Integrated Circuits Conference
ISSN（列印）	0886-5930

Conference

Conference	35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
國家/地區	美國
城市	San Jose, CA
期間	22/09/13 → 25/09/13

UN SDG

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存取文件

10.1109/CICC.2013.6658469

其它文件與鏈接

Link to publication in Scopus

引用此

Su, M. C., Chen, W.-Z., Wu, P. S., Chen, Y. H., Lee, C. C., & Jou, S.-J. (2013). A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. 於 Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013 文章 6658469 (Proceedings of the Custom Integrated Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2013.6658469

@inproceedings{75719f774b3545268dae0871acbc7b1c,

title = "A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression",

abstract = "A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UIpp input data jitter, the recovered clock jitter at 2GHz is 2.94psrms. The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200×150μm2.",

author = "Su, {Ming Chiuan} and Wei-Zen Chen and Wu, {Pei Si} and Chen, {Yu Hsian} and Lee, {Chao Cheng} and Shyh-Jye Jou",

year = "2013",

month = nov,

day = "7",

doi = "10.1109/CICC.2013.6658469",

language = "English",

isbn = "9781467361460",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013",

address = "美國",

note = "35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 ; Conference date: 22-09-2013 Through 25-09-2013",

}

Su, MC, Chen, W-Z, Wu, PS, Chen, YH, Lee, CC & Jou, S-J 2013, A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. 於 Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013., 6658469, Proceedings of the Custom Integrated Circuits Conference, Institute of Electrical and Electronics Engineers Inc., 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013, San Jose, CA, 美國, 22/09/13. https://doi.org/10.1109/CICC.2013.6658469

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. / Su, Ming Chiuan; Chen, Wei-Zen; Wu, Pei Si 等.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc., 2013. 6658469 (Proceedings of the Custom Integrated Circuits Conference).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression

AU - Su, Ming Chiuan

AU - Chen, Wei-Zen

AU - Wu, Pei Si

AU - Chen, Yu Hsian

AU - Lee, Chao Cheng

AU - Jou, Shyh-Jye

PY - 2013/11/7

Y1 - 2013/11/7

N2 - A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UIpp input data jitter, the recovered clock jitter at 2GHz is 2.94psrms. The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200×150μm2.

AB - A 10Gbps, 1/5-rate burst mode clock and data recovery (BMCDR) circuit is proposed. The BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneous phase-locking with jitter suppression for 10 GPON. Incorporating a 1/5-rate CDR with 1:5 demultiplexer, it achieves a high energy efficiency of 1.24pJ/bit. With a 4MHz, 0.22UIpp input data jitter, the recovered clock jitter at 2GHz is 2.94psrms. The prototype chip is fabricated in UMC 55nm CMOS technology. Chip size is 200×150μm2.

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DO - 10.1109/CICC.2013.6658469

M3 - Conference contribution

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SN - 9781467361460

T3 - Proceedings of the Custom Integrated Circuits Conference

BT - Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013

Y2 - 22 September 2013 through 25 September 2013

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Su MC, Chen WZ, Wu PS, Chen YH, Lee CC, Jou SJ. A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. 於 Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013. Institute of Electrical and Electronics Engineers Inc. 2013. 6658469. (Proceedings of the Custom Integrated Circuits Conference). doi: 10.1109/CICC.2013.6658469

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression

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