TY - GEN
T1 - A 10Bit, 10MS/s, low power cyclic ADC
AU - Chen, Chien Hung
AU - Chen, Wei-Zen
PY - 2013/9/9
Y1 - 2013/9/9
N2 - A low power, small form factor, cyclic ADC is proposed. By replacing the MDAC with an open loop residual amplifier, it relaxes the gain bandwidth requirement of the operational amplifier to save power. The residual amplifier is background calibrated without extra replica to avoid performance mismatches, and also save area and power. Timing reschedule scheme is proposed for each conversion step to accelerate conversion speed. At 10 MS/s operation, the corresponding FOM is 0.45pJ/conv.-step. Fabricated in a 85nm CMOS technology, the chip size is 0.077mm2.
AB - A low power, small form factor, cyclic ADC is proposed. By replacing the MDAC with an open loop residual amplifier, it relaxes the gain bandwidth requirement of the operational amplifier to save power. The residual amplifier is background calibrated without extra replica to avoid performance mismatches, and also save area and power. Timing reschedule scheme is proposed for each conversion step to accelerate conversion speed. At 10 MS/s operation, the corresponding FOM is 0.45pJ/conv.-step. Fabricated in a 85nm CMOS technology, the chip size is 0.077mm2.
KW - Background Calibration
KW - Cyclic ADC
KW - Residual Amplifier
UR - http://www.scopus.com/inward/record.url?scp=84883414739&partnerID=8YFLogxK
U2 - 10.1109/ICICDT.2013.6563326
DO - 10.1109/ICICDT.2013.6563326
M3 - Conference contribution
AN - SCOPUS:84883414739
SN - 9781467347419
T3 - ICICDT 2013 - International Conference on IC Design and Technology, Proceedings
SP - 155
EP - 158
BT - ICICDT 2013 - International Conference on IC Design and Technology, Proceedings
T2 - 2013 International Conference on IC Design and Technology, ICICDT 2013
Y2 - 29 May 2013 through 31 May 2013
ER -