@inproceedings{c8d5aec00ba944bc9138b560d5901adc,
title = "A 101-dB SFDR 98.5-dB DR 20-kHz BW Continuous Time Incremental Δ∑ ADC with FIR DAC and Robust Reset Timing for Sensor Interfaces",
abstract = "Incremental ΔΣ analog-to-digital converters are highly advantageous in sensor interface integrated circuits due to its ability to minimize latency and easily multiplex signals. This makes it a great choice for sensor interface applications. In this paper, a third-order continuous time incremental ADC is proposed, which incorporates circuit techniques such as chopping, FIR DAC and robust reset timing to achieve high resolution. The ADC is prototyped in 0.18 μm technology. This work can achieve a peak SNDR of 93.7dB, SFDR of 101dB with a 2.54 vpp input amplitude and a DR of 98.5dB, occupying an area of 0.197 mm2. This work consumes 342.8μW with 1.8V supply voltage and 20kHz bandwidth, resulting in a Schreier Figure of Merit (FoMs) of 176.1dB. It is highly suitable for sensor interface readout systems.",
keywords = "Analog-to-digital converter (ADC), chopper stabilization, continuous time (CT), finite impulse response (FIR), incremental, sensor",
author = "Wei, {Cheng En} and Wang, {Cheng Wei} and Hung, {Chen Hao} and Wang, {Chi Han} and Chou, {Chuan Tai} and Hung, {Duan Sin} and Lu, {Guan Wei} and Chen, {Chia Hung}",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 ; Conference date: 22-04-2024 Through 25-04-2024",
year = "2024",
doi = "10.1109/VLSITSA60681.2024.10546405",
language = "English",
series = "2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings",
address = "美國",
}