A 100-MHz Pipelined CMOS Comparator

Jieh-Tsorng Wu, Bruce A. Wooley

    研究成果: Article同行評審

    63 引文 斯高帕斯(Scopus)

    摘要

    This paper describes the design of a VLSI-compatible CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear “amplification” needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by means of a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8 bits, offset cancellation is incorporated in the first sense amplifier. In addition, an input sampling network comprised of only passive devices is used to sample the two analog inputs and cancel their common-mode voltage. The comparator has been integrated in a 2-üm CMOS technology and has a maximum sampling rate of over 100 MHz; it operates from a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate.

    原文English
    頁(從 - 到)1379-1385
    頁數7
    期刊IEEE Journal of Solid-State Circuits
    23
    發行號6
    DOIs
    出版狀態Published - 1 1月 1988

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