A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction

PLL-based frequency synthesizers with low phase noise and high frequency stability are essential for the next generation wireline and wireless communication systems. In the past, circuit techniques for in band noise suppression have drawn many research efforts, such as using reference injection [1] or phase noise cancellation through a delayed-discriminator based phase detector [3]. The injection locked PLLs (IL-PLL) count on a precise injection timing control to avoid generating high frequency spurs [1]. On the other hand, phase noise cancellation PLLs (PNC-PLL) require a sufficiently long delay time for the low frequency noise detection, and are more appealing for ring-oscillator based PLLs (RO-PLL) where the intrinsic in band noise is relatively high [3]. Both of them are limited by the noise floor of the reference signal, and cannot counteract critical aggressors close to or even higher than the reference frequencies that may encounter in SoC integration. To suppress the out band noise, active noise cancellation with extensive calibration is required [1][4]. The gain and delay matching between the aggressor and noise cancellation paths are vital to the existing techniques. Besides, it demands a stringently low noise level of the auxiliary circuitries to avoid deteriorating the in band noise floor.