A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converter

Fang Ting Chou, Zong Yi Chen, Chung-Chih Hung

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

This paper presents a 10-bit all binary-weighted current-steering digital-to-analog converter (DAC) with low-glitch and low-power properties. Instead of using large input buffers, the proposed design uses variable-delay buffers to compensate for the delay difference among different bits, and to reduce high glitch energy from 132pVs to 1.36pVs during major code transition. The spurious free dynamic range (SFDR) has been improved over 10dB compared to the conventional DAC without variable-delay buffers. This chip was implemented in a standard 0.18um CMOS process, and dissipates 19mW from a single 1.8V power supply.

原文English
主出版物標題International System on Chip Conference
編輯Kaijian Shi, Thomas Buchner, Danella Zhao, Ramalingam Sridhar
發行者IEEE Computer Society
頁面231-235
頁數5
ISBN(電子)9781479933785
DOIs
出版狀態Published - 5 11月 2014
事件27th IEEE International System on Chip Conference, SOCC 2014 - Las Vegas, United States
持續時間: 2 9月 20145 9月 2014

出版系列

名字International System on Chip Conference
ISSN(列印)2164-1676
ISSN(電子)2164-1706

Conference

Conference27th IEEE International System on Chip Conference, SOCC 2014
國家/地區United States
城市Las Vegas
期間2/09/145/09/14

指紋

深入研究「A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converter」主題。共同形成了獨特的指紋。

引用此