A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback

Yi Zhang, Chia Hung Chen, Tao He, Xin Meng, Nancy Qian, Ed Liu, Phillip Elliott, Gabor C. Temes

研究成果: Conference contribution同行評審

3 引文 斯高帕斯(Scopus)

摘要

A 3rd-order continuous-time ΔΣ modulator with a highly-digital excess loop delay compensation and multi-bit FIR feedback, to be used in an ultrasound beamformer, is presented. A digitally controlled reference switching matrix avoids the power-hungry adder, and allows a power-efficient design of the loop filter. A 2-bit 3-tap FIR feedback DAC optimally achieves lower sensitivity to clock jitter and applies reduced error signal to the loop filter, thus enhancing the loop filter linearity. The modulator operates at 1.2 GHz, and achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies 0.16 mm2 and dissipates 6.96mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

原文English
主出版物標題2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
發行者Institute of Electrical and Electronics Engineers Inc.
頁面321-324
頁數4
ISBN(電子)9781479940905
DOIs
出版狀態Published - 13 一月 2015
事件2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan
持續時間: 10 十一月 201412 十一月 2014

出版系列

名字2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
國家/地區Taiwan
城市Kaohsiung
期間10/11/1412/11/14

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