A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback

Yi Zhang; Chia Hung Chen; Tao He; Xin Meng; Nancy Qian; Ed Liu; Phillip Elliott; Gabor C. Temes

doi:10.1109/ASSCC.2014.7008925

A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback

Yi Zhang, Chia Hung Chen, Tao He, Xin Meng, Nancy Qian, Ed Liu, Phillip Elliott, Gabor C. Temes

電機工程學系

研究成果: Conference contribution › 同行評審

4 引文斯高帕斯（Scopus）

摘要

A 3^rd-order continuous-time ΔΣ modulator with a highly-digital excess loop delay compensation and multi-bit FIR feedback, to be used in an ultrasound beamformer, is presented. A digitally controlled reference switching matrix avoids the power-hungry adder, and allows a power-efficient design of the loop filter. A 2-bit 3-tap FIR feedback DAC optimally achieves lower sensitivity to clock jitter and applies reduced error signal to the loop filter, thus enhancing the loop filter linearity. The modulator operates at 1.2 GHz, and achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies 0.16 mm² and dissipates 6.96mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

原文	English
主出版物標題	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	321-324
頁數	4
ISBN（電子）	9781479940905
DOIs	https://doi.org/10.1109/ASSCC.2014.7008925
出版狀態	Published - 13 1月 2015
事件	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 - Kaohsiung, Taiwan 持續時間: 10 11月 2014 → 12 11月 2014

出版系列

名字	2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Conference

Conference	2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014
國家/地區	Taiwan
城市	Kaohsiung
期間	10/11/14 → 12/11/14

存取文件

10.1109/ASSCC.2014.7008925

其它文件與鏈接

Link to publication in Scopus

引用此

Zhang, Y., Chen, C. H., He, T., Meng, X., Qian, N., Liu, E., Elliott, P., & Temes, G. C. (2015). A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback. 於 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers (頁 321-324). Article 7008925 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASSCC.2014.7008925

Zhang, Yi ; Chen, Chia Hung ; He, Tao 等. / A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback. 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. 頁 321-324 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

@inproceedings{c2a15c60bbbe4eaf9a1c0a1bf56a0da6,

title = "A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback",

abstract = "A 3rd-order continuous-time ΔΣ modulator with a highly-digital excess loop delay compensation and multi-bit FIR feedback, to be used in an ultrasound beamformer, is presented. A digitally controlled reference switching matrix avoids the power-hungry adder, and allows a power-efficient design of the loop filter. A 2-bit 3-tap FIR feedback DAC optimally achieves lower sensitivity to clock jitter and applies reduced error signal to the loop filter, thus enhancing the loop filter linearity. The modulator operates at 1.2 GHz, and achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies 0.16 mm2 and dissipates 6.96mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.",

author = "Yi Zhang and Chen, {Chia Hung} and Tao He and Xin Meng and Nancy Qian and Ed Liu and Phillip Elliott and Temes, {Gabor C.}",

year = "2015",

month = jan,

day = "13",

doi = "10.1109/ASSCC.2014.7008925",

language = "English",

series = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "321--324",

booktitle = "2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers",

address = "United States",

note = "2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 ; Conference date: 10-11-2014 Through 12-11-2014",

}

Zhang, Y, Chen, CH, He, T, Meng, X, Qian, N, Liu, E, Elliott, P & Temes, GC 2015, A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback. 於 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers., 7008925, 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers, Institute of Electrical and Electronics Engineers Inc., 頁 321-324, 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, Kaohsiung, Taiwan, 10/11/14. https://doi.org/10.1109/ASSCC.2014.7008925

A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback. / Zhang, Yi; Chen, Chia Hung; He, Tao 等.
2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. 321-324 7008925 (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback

AU - Zhang, Yi

AU - Chen, Chia Hung

AU - He, Tao

AU - Meng, Xin

AU - Qian, Nancy

AU - Liu, Ed

AU - Elliott, Phillip

AU - Temes, Gabor C.

PY - 2015/1/13

Y1 - 2015/1/13

N2 - A 3rd-order continuous-time ΔΣ modulator with a highly-digital excess loop delay compensation and multi-bit FIR feedback, to be used in an ultrasound beamformer, is presented. A digitally controlled reference switching matrix avoids the power-hungry adder, and allows a power-efficient design of the loop filter. A 2-bit 3-tap FIR feedback DAC optimally achieves lower sensitivity to clock jitter and applies reduced error signal to the loop filter, thus enhancing the loop filter linearity. The modulator operates at 1.2 GHz, and achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies 0.16 mm2 and dissipates 6.96mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

AB - A 3rd-order continuous-time ΔΣ modulator with a highly-digital excess loop delay compensation and multi-bit FIR feedback, to be used in an ultrasound beamformer, is presented. A digitally controlled reference switching matrix avoids the power-hungry adder, and allows a power-efficient design of the loop filter. A 2-bit 3-tap FIR feedback DAC optimally achieves lower sensitivity to clock jitter and applies reduced error signal to the loop filter, thus enhancing the loop filter linearity. The modulator operates at 1.2 GHz, and achieves 79.4 dB dynamic range, 77.3 dB SNR and 74.3 dB SNDR over a 15 MHz signal bandwidth. Fabricated in a 65 nm CMOS process, the core modulator occupies 0.16 mm2 and dissipates 6.96mW from a 1 V supply. A 58.6 fJ/conversion-step figure of merit is achieved.

UR - http://www.scopus.com/inward/record.url?scp=84922541144&partnerID=8YFLogxK

U2 - 10.1109/ASSCC.2014.7008925

DO - 10.1109/ASSCC.2014.7008925

M3 - Conference contribution

AN - SCOPUS:84922541144

T3 - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

SP - 321

EP - 324

BT - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 10th IEEE Asian Solid-State Circuits Conference, A-SSCC 2014

Y2 - 10 November 2014 through 12 November 2014

ER -

Zhang Y, Chen CH, He T, Meng X, Qian N, Liu E 等. A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback. 於 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. 321-324. 7008925. (2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers). doi: 10.1109/ASSCC.2014.7008925

A 1 v 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback

摘要

出版系列

Conference

存取文件

其它文件與鏈接

指紋

引用此