A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique

Chun-Yu Lin; Tun-Ju Wang; Yu-Ting Hung; Tsung-Hsien Lin

doi:10.1109/VLSI-DAT49148.2020.9196213

A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique

Chun-Yu Lin, Tun-Ju Wang, Yu-Ting Hung, Tsung-Hsien Lin^*

^*此作品的通信作者

影像與生醫光電研究所

研究成果: Conference contribution › 同行評審

1 引文斯高帕斯（Scopus）

摘要

An open-loop fractional output divider (FOD) using phase rotating technique is presented. A phase rotating technique is adopted to reduce the dynamic range of digital-to-time converter (DTC) for output jitter improvement. This prototype is implemented in a 90-nm CMOS process. It can operate over a frequency range of 0.635 MHz to 162.5 MHz. At 160-MHz output frequency, it consumes 6.29 mW from 1-V supply. The measured phase noises at 1-MHz offset is - 135.8 dBc/Hz and it achieves 1.19 ps(rms) integrated jitter (10 kHz to 30 MHz).

原文	English
主出版物標題	2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)
發行者	IEEE
頁數	2
DOIs	https://doi.org/10.1109/VLSI-DAT49148.2020.9196213
出版狀態	Published - 8月 2020
事件	International Symposium on VLSI Design, Automation and Test (VLSI-DAT) - Hsinchu 持續時間: 25 4月 2016 → 27 4月 2016

出版系列

名字	International Symposium on VLSI Design Automation and Test
發行者	IEEE
ISSN（列印）	2474-2724

Conference

Conference	International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
城市	Hsinchu
期間	25/04/16 → 27/04/16

存取文件

10.1109/VLSI-DAT49148.2020.9196213

引用此

@inproceedings{aeb1cd7773884e0abd48e346edc98507,

title = "A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique",

abstract = "An open-loop fractional output divider (FOD) using phase rotating technique is presented. A phase rotating technique is adopted to reduce the dynamic range of digital-to-time converter (DTC) for output jitter improvement. This prototype is implemented in a 90-nm CMOS process. It can operate over a frequency range of 0.635 MHz to 162.5 MHz. At 160-MHz output frequency, it consumes 6.29 mW from 1-V supply. The measured phase noises at 1-MHz offset is - 135.8 dBc/Hz and it achieves 1.19 ps(rms) integrated jitter (10 kHz to 30 MHz).",

keywords = "fractional output divider, phase rotating technique",

author = "Chun-Yu Lin and Tun-Ju Wang and Yu-Ting Hung and Tsung-Hsien Lin",

year = "2020",

month = aug,

doi = "10.1109/VLSI-DAT49148.2020.9196213",

language = "English",

series = "International Symposium on VLSI Design Automation and Test",

publisher = "IEEE",

booktitle = "2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)",

note = "International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ; Conference date: 25-04-2016 Through 27-04-2016",

}

Lin, C-Y, Wang, T-J, Hung, Y-T & Lin, T-H 2020, A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique. 於 2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT). International Symposium on VLSI Design Automation and Test, IEEE, International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, 25/04/16. https://doi.org/10.1109/VLSI-DAT49148.2020.9196213

TY - GEN

T1 - A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique

AU - Lin, Chun-Yu

AU - Wang, Tun-Ju

AU - Hung, Yu-Ting

AU - Lin, Tsung-Hsien

PY - 2020/8

Y1 - 2020/8

N2 - An open-loop fractional output divider (FOD) using phase rotating technique is presented. A phase rotating technique is adopted to reduce the dynamic range of digital-to-time converter (DTC) for output jitter improvement. This prototype is implemented in a 90-nm CMOS process. It can operate over a frequency range of 0.635 MHz to 162.5 MHz. At 160-MHz output frequency, it consumes 6.29 mW from 1-V supply. The measured phase noises at 1-MHz offset is - 135.8 dBc/Hz and it achieves 1.19 ps(rms) integrated jitter (10 kHz to 30 MHz).

AB - An open-loop fractional output divider (FOD) using phase rotating technique is presented. A phase rotating technique is adopted to reduce the dynamic range of digital-to-time converter (DTC) for output jitter improvement. This prototype is implemented in a 90-nm CMOS process. It can operate over a frequency range of 0.635 MHz to 162.5 MHz. At 160-MHz output frequency, it consumes 6.29 mW from 1-V supply. The measured phase noises at 1-MHz offset is - 135.8 dBc/Hz and it achieves 1.19 ps(rms) integrated jitter (10 kHz to 30 MHz).

KW - fractional output divider

KW - phase rotating technique

U2 - 10.1109/VLSI-DAT49148.2020.9196213

DO - 10.1109/VLSI-DAT49148.2020.9196213

M3 - Conference contribution

T3 - International Symposium on VLSI Design Automation and Test

BT - 2020 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT)

PB - IEEE

T2 - International Symposium on VLSI Design, Automation and Test (VLSI-DAT)

Y2 - 25 April 2016 through 27 April 2016

ER -

A 1-200MHz Multiple Output Fractional Divider Using Phase Rotating Technique

摘要

出版系列

Conference

存取文件

指紋

引用此