A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application

Shao Wei Yen; Ming Chih Hu; Chih Lung Chen; Hsie-Chia Chang; Shyh-Jye Jou; Chen-Yi Lee

doi:10.1109/CICC.2009.5280876

A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application

Shao Wei Yen^*, Ming Chih Hu, Chih Lung Chen, Hsie-Chia Chang, Shyh-Jye Jou, Chen-Yi Lee

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

摘要

An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a division-free reconfigurable interleaver architecture is implemented by simple addition and subtraction instead of division. Fabricated with the 90nm CMOS process, the proposed CTC decoder chip which occupies core area of 0.92mm² can achieve 30Mb/s with 23.4mW power consumption.

原文	English
主出版物標題	2009 IEEE Custom Integrated Circuits Conference, CICC '09
發行者	IEEE
頁面	191-194
頁數	4
ISBN（列印）	9781424440726
DOIs	https://doi.org/10.1109/CICC.2009.5280876
出版狀態	Published - 1 12月 2009
事件	2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States 持續時間: 13 9月 2009 → 16 9月 2009

出版系列

名字	Proceedings of the Custom Integrated Circuits Conference
ISSN（列印）	0886-5930

Conference

Conference	2009 IEEE Custom Integrated Circuits Conference, CICC '09
國家/地區	United States
城市	San Jose, CA
期間	13/09/09 → 16/09/09

存取文件

10.1109/CICC.2009.5280876

其它文件與鏈接

Link to publication in Scopus

引用此

@inproceedings{8cd8a81778ce4ae691e74d65f87e8e16,

title = "A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application",

abstract = "An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a division-free reconfigurable interleaver architecture is implemented by simple addition and subtraction instead of division. Fabricated with the 90nm CMOS process, the proposed CTC decoder chip which occupies core area of 0.92mm2 can achieve 30Mb/s with 23.4mW power consumption.",

author = "Yen, {Shao Wei} and Hu, {Ming Chih} and Chen, {Chih Lung} and Hsie-Chia Chang and Shyh-Jye Jou and Chen-Yi Lee",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/CICC.2009.5280876",

language = "English",

isbn = "9781424440726",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "IEEE",

pages = "191--194",

booktitle = "2009 IEEE Custom Integrated Circuits Conference, CICC '09",

note = "null ; Conference date: 13-09-2009 Through 16-09-2009",

}

Yen, SW, Hu, MC, Chen, CL, Chang, H-C , Jou, S-J & Lee, C-Y 2009, A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application. 於 2009 IEEE Custom Integrated Circuits Conference, CICC '09., 5280876, Proceedings of the Custom Integrated Circuits Conference, IEEE, 頁 191-194, 2009 IEEE Custom Integrated Circuits Conference, CICC '09, San Jose, CA, United States, 13/09/09. https://doi.org/10.1109/CICC.2009.5280876

TY - GEN

T1 - A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application

AU - Yen, Shao Wei

AU - Hu, Ming Chih

AU - Chen, Chih Lung

AU - Chang, Hsie-Chia

AU - Jou, Shyh-Jye

AU - Lee, Chen-Yi

PY - 2009/12/1

Y1 - 2009/12/1

N2 - An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a division-free reconfigurable interleaver architecture is implemented by simple addition and subtraction instead of division. Fabricated with the 90nm CMOS process, the proposed CTC decoder chip which occupies core area of 0.92mm2 can achieve 30Mb/s with 23.4mW power consumption.

AB - An area-efficient and fully-compliant decoder for convolutional turbo code (CTC) of WiMAX 802.16e is presented. The proposed decoder can support all 17 modes specified in IEEE 802.16e system. By scaling the extrinsic information, the Max-Log MAP algorithm is used to reduce the hardware complexity with the minimized performance loss. A two-phase extrinsic memory and reversed sliding window technique are demonstrated for less memory requirement and decoding latency. Moreover, a division-free reconfigurable interleaver architecture is implemented by simple addition and subtraction instead of division. Fabricated with the 90nm CMOS process, the proposed CTC decoder chip which occupies core area of 0.92mm2 can achieve 30Mb/s with 23.4mW power consumption.

UR - http://www.scopus.com/inward/record.url?scp=74049083300&partnerID=8YFLogxK

U2 - 10.1109/CICC.2009.5280876

DO - 10.1109/CICC.2009.5280876

M3 - Conference contribution

AN - SCOPUS:74049083300

SN - 9781424440726

T3 - Proceedings of the Custom Integrated Circuits Conference

SP - 191

EP - 194

BT - 2009 IEEE Custom Integrated Circuits Conference, CICC '09

PB - IEEE

Y2 - 13 September 2009 through 16 September 2009

ER -

A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application

摘要

出版系列

Conference

存取文件

其它文件與鏈接

指紋

引用此