TY - GEN
T1 - A 0.6-7 Gbps, 1/7 rate, burst mode clock and data recovery circuit and demultiplexer
AU - Chen, Yu Hsian
AU - Chen, Wei-Zen
PY - 2012/9/28
Y1 - 2012/9/28
N2 - A 1/7 rate, burst mode clock and data recovery circuit incorporating with demultiplexer is proposed. It covers 622 Mbps to 7 Gbps operation by selective-gating digitally controlled oscillator for phase synchronization and digital frequency-locked loop for frequency tracking. The latency for data recovery and 1:7 demultiplexing is less than 10 bit periods. Incorporating both CDR and demultiplexer, this chip consumes 1.5 mW, 6 mW, and 17 mW respectively at 622 Mbps, 2488Mbps, and 7Gbps operations. Implemented in a 90 nm CMOS technology, the chip area is 1.162 × 1.205 mm
2.
AB - A 1/7 rate, burst mode clock and data recovery circuit incorporating with demultiplexer is proposed. It covers 622 Mbps to 7 Gbps operation by selective-gating digitally controlled oscillator for phase synchronization and digital frequency-locked loop for frequency tracking. The latency for data recovery and 1:7 demultiplexing is less than 10 bit periods. Incorporating both CDR and demultiplexer, this chip consumes 1.5 mW, 6 mW, and 17 mW respectively at 622 Mbps, 2488Mbps, and 7Gbps operations. Implemented in a 90 nm CMOS technology, the chip area is 1.162 × 1.205 mm
2.
KW - digital controlled oscillator
KW - frequency locked loop
KW - phase locked loop
UR - http://www.scopus.com/inward/record.url?scp=84866610233&partnerID=8YFLogxK
U2 - 10.1109/RFIC.2012.6242339
DO - 10.1109/RFIC.2012.6242339
M3 - Conference contribution
AN - SCOPUS:84866610233
SN - 9781467304146
T3 - Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
SP - 531
EP - 534
BT - 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012 - Digest of Papers
T2 - 2012 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2012
Y2 - 17 June 2012 through 19 June 2012
ER -