@inproceedings{f81a8eabb80640f0ac214999660ca1e7,
title = "A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter",
abstract = "This paper presents the design of an ultra-low voltage (ULV), time-based, continuous-time ΔΣ analog-to-digital data converter. By replacing the 2nd stage integrator with frequency-calibrated voltage bootstrapping VCO, it circumvents ULV design challenges while achieving a signal bandwidth up to 2 MHz. Back-gate adder, voltage amplifier, and bootstrapping logic cells are also proposed to enable 250 MHz sampling rate operation. The measured peak SNDR is 53 dB under a supply voltage of 0.4 V. The whole ADC consumes 526 μW. Fabricated in a 90 nm CMOS process, the core area is 0.08 mm2.",
keywords = "CT-ΔΣ ADC, ULP, ULV",
author = "Chen, {Hung Kai} and Wei-Zen Chen and Zhiyuan Ren",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 ; Conference date: 03-11-2015 Through 06-11-2015",
year = "2016",
month = jul,
day = "21",
doi = "10.1109/ASICON.2015.7517109",
language = "English",
series = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
editor = "Junyan Ren and Ting-Ao Tang and Fan Ye and Huihua Yu",
booktitle = "Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015",
address = "United States",
}