A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2μW to 50μW

Xin Zhang; Po-Hung Chen; Yoshikatsu Ryu; Koichi Ishida; Yasuyuki Okuma; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya

doi:10.1109/VLSIC.2012.6243856

A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2μW to 50μW

Xin Zhang^*, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

16 引文斯高帕斯（Scopus）

摘要

A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed.

原文	English
主出版物標題	2012 Symposium on VLSI Circuits, VLSIC 2012
頁面	194-195
頁數	2
DOIs	https://doi.org/10.1109/VLSIC.2012.6243856
出版狀態	Published - 28 9月 2012
事件	2012 Symposium on VLSI Circuits, VLSIC 2012 - Honolulu, HI, United States 持續時間: 13 6月 2012 → 15 6月 2012

出版系列

名字	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2012 Symposium on VLSI Circuits, VLSIC 2012
國家/地區	United States
城市	Honolulu, HI
期間	13/06/12 → 15/06/12

存取文件

10.1109/VLSIC.2012.6243856

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Link to publication in Scopus

引用此

Zhang, X., Chen, P-H., Ryu, Y., Ishida, K., Okuma, Y., Watanabe, K., Sakurai, T., & Takamiya, M. (2012). A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2μW to 50μW. 於 2012 Symposium on VLSI Circuits, VLSIC 2012 (頁 194-195). [6243856] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). https://doi.org/10.1109/VLSIC.2012.6243856

@inproceedings{556d699b62cb4fcc95471642a9f53862,

title = "A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2μW to 50μW",

abstract = "A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed.",

author = "Xin Zhang and Po-Hung Chen and Yoshikatsu Ryu and Koichi Ishida and Yasuyuki Okuma and Kazunori Watanabe and Takayasu Sakurai and Makoto Takamiya",

year = "2012",

month = sep,

day = "28",

doi = "10.1109/VLSIC.2012.6243856",

language = "English",

isbn = "9781467308458",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "194--195",

booktitle = "2012 Symposium on VLSI Circuits, VLSIC 2012",

note = "null ; Conference date: 13-06-2012 Through 15-06-2012",

}

Zhang, X, Chen, P-H, Ryu, Y, Ishida, K, Okuma, Y, Watanabe, K, Sakurai, T & Takamiya, M 2012, A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2μW to 50μW. 於 2012 Symposium on VLSI Circuits, VLSIC 2012., 6243856, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, 頁 194-195, 2012 Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, United States, 13/06/12. https://doi.org/10.1109/VLSIC.2012.6243856

A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2μW to 50μW. / Zhang, Xin; Chen, Po-Hung; Ryu, Yoshikatsu 等.

2012 Symposium on VLSI Circuits, VLSIC 2012. 2012. p. 194-195 6243856 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution › 同行評審

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AU - Ishida, Koichi

AU - Okuma, Yasuyuki

AU - Watanabe, Kazunori

AU - Sakurai, Takayasu

AU - Takamiya, Makoto

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A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2μW to 50μW

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Conference

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