A 0.3 V 10b 3 MS/s SAR ADC with Comparator Calibration and Kickback Noise Reduction for Biomedical Applications

Chung Chih Hung*, Shih Hsing Wang

*此作品的通信作者

研究成果: Chapter同行評審

摘要

This chapter presents a 10-bit successive approximation analog-to-digital converter (ADC) that operates at an ultralow voltage of 0.3 V and can be applied to biomedical implants. The study proposes several techniques to improve the ADC performance. A pipeline comparator was utilized to maintain the advantages of dynamic comparators and reduce the kickback noise. Weight biasing calibration was used to correct the offset voltage without degrading the operating speed of the comparator. The incorporation of a unity-gain buffer improved the bootstrap switch leakage problem during the hold period and reduced the effect of parasitic capacitances on the digital-to-analog converter. The chip was fabricated using 90-nm CMOS technology. The data measured at a supply voltage of 0.3 V and sampling rate of 3 MSps for differential nonlinearity and integral nonlinearity were +0.83/−0.54 and +0.84/−0.89, respectively, and the signal-to-noise plus distortion ratio and effective number of bits were 56.42 dB and 9.08 b, respectively. The measured total power consumption was 6.6 μW at a figure of merit of 4.065 fJ/conv.-step.

原文English
主出版物標題Analog Circuits and Signal Processing
發行者Springer
頁面193-213
頁數21
DOIs
出版狀態Published - 2022

出版系列

名字Analog Circuits and Signal Processing
ISSN(列印)1872-082X
ISSN(電子)2197-1854

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