A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver

Cheng Chi Wong; Cheng Hao Tang; Ming Wei Lai; Yan Xiu Zheng; Chien Ching Lin; Hsie-Chia Chang; Chen-Yi Lee; Yu-Ted Su

doi:10.1109/CICC.2007.4405731

A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver

Cheng Chi Wong, Cheng Hao Tang, Ming Wei Lai, Yan Xiu Zheng, Chien Ching Lin, Hsie-Chia Chang, Chen-Yi Lee, Yu-Ted Su

電機工程學系

研究成果: Conference contribution › 同行評審

5 引文斯高帕斯（Scopus）

摘要

This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 × 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 μm CMOS process, the test results show the energy efficiency is 0.22 nJ/b/iter in the 160 Mb/s data rate.

原文	American English
主出版物標題	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
發行者	Institute of Electrical and Electronics Engineers Inc.
頁面	273-276
頁數	4
ISBN（電子）	1424407869, 9781424407866
DOIs	https://doi.org/10.1109/CICC.2007.4405731
出版狀態	Published - 16 9月 2007
事件	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States 持續時間: 16 9月 2007 → 19 9月 2007

出版系列

名字	Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Conference

Conference	29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
國家/地區	United States
城市	San Jose
期間	16/09/07 → 19/09/07

UN SDG

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10.1109/CICC.2007.4405731

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Link to publication in Scopus

引用此

Wong, C. C., Tang, C. H., Lai, M. W., Zheng, Y. X., Lin, C. C., Chang, H-C., Lee, C-Y., & Su, Y-T. (2007). A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver. 於 Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007 (頁 273-276). 文章 4405731 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2007.4405731

Wong, Cheng Chi ; Tang, Cheng Hao ; Lai, Ming Wei 等. / A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver. Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. 頁 273-276 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

@inproceedings{82fbcf1a1c9b4d7f8ca0670620cfa9a3,

title = "A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver",

abstract = "This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 × 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 μm CMOS process, the test results show the energy efficiency is 0.22 nJ/b/iter in the 160 Mb/s data rate.",

author = "Wong, {Cheng Chi} and Tang, {Cheng Hao} and Lai, {Ming Wei} and Zheng, {Yan Xiu} and Lin, {Chien Ching} and Hsie-Chia Chang and Chen-Yi Lee and Yu-Ted Su",

year = "2007",

month = sep,

day = "16",

doi = "10.1109/CICC.2007.4405731",

language = "American English",

series = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "273--276",

booktitle = "Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007",

address = "United States",

note = "29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 ; Conference date: 16-09-2007 Through 19-09-2007",

}

Wong, CC, Tang, CH, Lai, MW, Zheng, YX, Lin, CC, Chang, H-C , Lee, C-Y & Su, Y-T 2007, A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver. 於 Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007., 4405731, Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007, Institute of Electrical and Electronics Engineers Inc., 頁 273-276, 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007, San Jose, United States, 16/09/07. https://doi.org/10.1109/CICC.2007.4405731

A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver. / Wong, Cheng Chi; Tang, Cheng Hao; Lai, Ming Wei 等.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc., 2007. p. 273-276 4405731 (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver

AU - Wong, Cheng Chi

AU - Tang, Cheng Hao

AU - Lai, Ming Wei

AU - Zheng, Yan Xiu

AU - Lin, Chien Ching

AU - Chang, Hsie-Chia

AU - Lee, Chen-Yi

AU - Su, Yu-Ted

PY - 2007/9/16

Y1 - 2007/9/16

N2 - This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 × 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 μm CMOS process, the test results show the energy efficiency is 0.22 nJ/b/iter in the 160 Mb/s data rate.

AB - This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 × 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 μm CMOS process, the test results show the energy efficiency is 0.22 nJ/b/iter in the 160 Mb/s data rate.

UR - http://www.scopus.com/inward/record.url?scp=48849098698&partnerID=8YFLogxK

U2 - 10.1109/CICC.2007.4405731

DO - 10.1109/CICC.2007.4405731

M3 - Conference contribution

AN - SCOPUS:48849098698

T3 - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

SP - 273

EP - 276

BT - Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007

Y2 - 16 September 2007 through 19 September 2007

ER -

Wong CC, Tang CH, Lai MW, Zheng YX, Lin CC, Chang H-C 等. A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver. 於 Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007. Institute of Electrical and Electronics Engineers Inc. 2007. p. 273-276. 4405731. (Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007). doi: 10.1109/CICC.2007.4405731

A 0.22 nJ/b/ITER 0.13 μm turbo decoder chip using inter-block permutation interleaver

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