A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector

Keyphrases

• Cell-based 100%
• All-digital Phase-locked Loop (ADPLL) 100%
• Phase Detector 100%
• Fractional-N 100%
• CMOS Technology 50%
• Time-to-digital Converter 50%
• Linear Phase 50%
• Chip Size 50%
• Feedback Path 50%
• RMS Jitter 50%
• Phase Detection 50%
• Multiplication Factor 50%
• Zero-stabilization 50%
• Phase Quantization Error 50%
• Additional Feedback 50%
• Reference Phase 50%

Engineering

• Phase Locked Loop 100%
• Phase Detector 100%
• Digital Converter 50%
• Linear Phase 50%
• Feedback Path 50%
• Phase Error 50%
• Rms Jitter 50%
• Multiplication Factor 50%