@inproceedings{24abffa97ce4463b823a17692eb06d7f,
title = "A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector",
abstract = "A 0.1-3 GHz, cell-based, fractional-N ADPLL with ΔΣ noise-shaped phase detector is presented. By dithering the reference phase and quantization phase error through an additional feedback path, linear phase detection and zero stabilization are accomplished without resort to sophisticated time to digital converter (TDC). The measured rms jitter from a 3GHz carrier is 1.9 ps with a multiplication factor of 60. Implemented in TSMC 40nm general purpose superb CMOS technology, the chip size is 280um × 240um.",
keywords = "fractional-N ADPLL, TDC, ΔΣ phase detector",
author = "Liu, {Yao Chia} and Wei-Zen Chen and Chou, {Mao Hsuan} and Tsai, {Tsung Hsien} and Lee, {Yen Wei} and Yuan, {Min Shueh}",
year = "2013",
month = nov,
day = "7",
doi = "10.1109/CICC.2013.6658528",
language = "English",
isbn = "9781467361460",
series = "Proceedings of the Custom Integrated Circuits Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013",
address = "United States",
note = "35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 ; Conference date: 22-09-2013 Through 25-09-2013",
}