@inproceedings{1f332f56ff424d339d9f3694f61fc28b,
title = "A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement",
abstract = "A sub-ps ΔΣ TDC for PLL built-in phase noise measurement is proposed. Integrated with a 4.8 GHz PLL, the measured rms jitter integrated from 1kHz to 100 MHz by using spectrum analyzer E4448A and ΔΣ TDC are 1.46 ps and 1.39 ps respectively, which manifests less than 5% discrepancy. The BIST circuit consumes 3mW from a 1.2V supply. Fabricated in TSMC 65nm CMOS process, the chip area is only 0.03mm2.",
keywords = "BIST, PLL, Phase Noise Measurement, sub-ps ΔΣ TDC",
author = "Wei-Zen Chen and Kuo, {Po I.}",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 42nd European Solid-State Circuits Conference, ESSCIRC 2016 ; Conference date: 12-09-2016 Through 15-09-2016",
year = "2016",
month = oct,
day = "18",
doi = "10.1109/ESSCIRC.2016.7598313",
language = "English",
series = "European Solid-State Circuits Conference",
publisher = "IEEE Computer Society",
pages = "347--350",
booktitle = "ESSCIRC 2016",
address = "United States",
}