8T Single-ended sub-threshold SRAM with cross-point data-aware write operation

Yi Wei Chiu*, Jihi Yu Lin, Ming Hsien Tu, Shyh-Jye Jou, Ching Te Chuang

*此作品的通信作者

    研究成果: Conference contribution同行評審

    20 引文 斯高帕斯(Scopus)

    摘要

    This paper presents a new 8T SRAM cell with data-aware cross-point Write operation and series connected Read buffer for low power and low voltage operation. The cell features a shared footer device to control the VGND for cell pass-gate (Write) transistors and the Read buffer. The row-based VGND control and the column-based data-aware Write Word-Line form a cross-point Write structure, thus eliminating Write Half-Select Disturb to facilitate bit-interleaving architecture. Replica based timing tracking circuit is used to control the pulse width of Word-Line Enable (WLE) signal to overcome the large timing variation at low voltage and to reduce the Word-Line active power consumption. A 4Kbit SRAM test chip implemented in 90nm HVT CMOS technology operates at 120MHz at 0.6V and 6MHz at 0.38V with measured power consumption of 2.99uW at 6MHz, 0.38V.

    原文English
    主出版物標題IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
    頁面169-174
    頁數6
    DOIs
    出版狀態Published - 19 9月 2011
    事件17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka, Japan
    持續時間: 1 8月 20113 8月 2011

    出版系列

    名字Proceedings of the International Symposium on Low Power Electronics and Design
    ISSN(列印)1533-4678

    Conference

    Conference17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
    國家/地區Japan
    城市Fukuoka
    期間1/08/113/08/11

    指紋

    深入研究「8T Single-ended sub-threshold SRAM with cross-point data-aware write operation」主題。共同形成了獨特的指紋。

    引用此