8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips

Jian Wei Su; Pei Jung Lu; Ping Chun Wu; Yen Chi Chou; Ta Wei Liu; Yen Lin Chung; Li Yang Hung; Jin Sheng Ren; Wei Hsing Huang; Chih Han Chien; Peng I. Mei; Sih Han Li; Shyh Shyuan Sheu; Wei Chung Lo; Shih Chieh Chang; Hao Chiao Hong; Chung Chuan Lo; Ren Shuo Liu; Chih Cheng Hsieh; Kea Tiong Tang; Meng Fan Chang

doi:10.1109/TCSII.2023.3331375

8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips

Jian Wei Su, Pei Jung Lu, Ping Chun Wu, Yen Chi Chou, Ta Wei Liu, Yen Lin Chung, Li Yang Hung, Jin Sheng Ren, Wei Hsing Huang, Chih Han Chien, Peng I. Mei, Sih Han Li, Shyh Shyuan Sheu, Wei Chung Lo, Shih Chieh Chang, Hao Chiao Hong, Chung Chuan Lo, Ren Shuo Liu, Chih Cheng Hsieh, Kea Tiong TangMeng Fan Chang^*

^*此作品的通信作者

電機工程學系

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

摘要

Efforts to advance the use of analog SRAM compute-in-memory (SRAM-CIM) macros for high-precision multiply-and-accumulate (MAC) operations must deal with issues pertaining to energy efficiency, computing latency (T_AC), and area overhead. This brief presents a novel SRAM-CIM structure that utilizes (1) a high input precision computing cell (HIPCC) to perform 8b-MAC operations with high multiplication throughput, and (2) a global bitline-combining (GBL-comb) scheme to improve energy efficiency by reducing the number of analog-to-digital converters (ADCs). A 28nm 384-kb SRAM-CIM macro with 20-bit output precision (near-full precision) was fabricated using a foundry-provided 28nm logic process for MAC operations with 8b-input, 8b-weight, and 16 accumulations. The resulting macro achieved a T_AC of 3.6 ns with energy efficiency of 14.97 TOPS/W when applied to 8-bit MAC operations.

原文	English
頁（從 - 到）	2304-2308
頁數	5
期刊	IEEE Transactions on Circuits and Systems I: Regular Papers
卷	71
發行號	4
DOIs	https://doi.org/10.1109/TCSII.2023.3331375
出版狀態	Published - 4月 2024

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Su, J. W., Lu, P. J., Wu, P. C., Chou, Y. C., Liu, T. W., Chung, Y. L., Hung, L. Y., Ren, J. S., Huang, W. H., Chien, C. H., Mei, P. I., Li, S. H., Sheu, S. S., Lo, W. C., Chang, S. C., Hong, H. C., Lo, C. C., Liu, R. S., Hsieh, C. C., ... Chang, M. F. (2024). 8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Transactions on Circuits and Systems I: Regular Papers, 71(4), 2304-2308. https://doi.org/10.1109/TCSII.2023.3331375

@article{bda9098ba14743778448de5bec72899a,

title = "8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips",

abstract = "Efforts to advance the use of analog SRAM compute-in-memory (SRAM-CIM) macros for high-precision multiply-and-accumulate (MAC) operations must deal with issues pertaining to energy efficiency, computing latency (TAC), and area overhead. This brief presents a novel SRAM-CIM structure that utilizes (1) a high input precision computing cell (HIPCC) to perform 8b-MAC operations with high multiplication throughput, and (2) a global bitline-combining (GBL-comb) scheme to improve energy efficiency by reducing the number of analog-to-digital converters (ADCs). A 28nm 384-kb SRAM-CIM macro with 20-bit output precision (near-full precision) was fabricated using a foundry-provided 28nm logic process for MAC operations with 8b-input, 8b-weight, and 16 accumulations. The resulting macro achieved a TAC of 3.6 ns with energy efficiency of 14.97 TOPS/W when applied to 8-bit MAC operations.",

keywords = "Artificial intelligence (AI), computing-in-memory (CIM), inference, local computing cell (LCC), static random-access memory (SRAM)",

author = "Su, {Jian Wei} and Lu, {Pei Jung} and Wu, {Ping Chun} and Chou, {Yen Chi} and Liu, {Ta Wei} and Chung, {Yen Lin} and Hung, {Li Yang} and Ren, {Jin Sheng} and Huang, {Wei Hsing} and Chien, {Chih Han} and Mei, {Peng I.} and Li, {Sih Han} and Sheu, {Shyh Shyuan} and Lo, {Wei Chung} and Chang, {Shih Chieh} and Hong, {Hao Chiao} and Lo, {Chung Chuan} and Liu, {Ren Shuo} and Hsieh, {Chih Cheng} and Tang, {Kea Tiong} and Chang, {Meng Fan}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.",

year = "2024",

month = apr,

doi = "10.1109/TCSII.2023.3331375",

language = "English",

volume = "71",

pages = "2304--2308",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1549-7747",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

Su, JW, Lu, PJ, Wu, PC, Chou, YC, Liu, TW, Chung, YL, Hung, LY, Ren, JS, Huang, WH, Chien, CH, Mei, PI, Li, SH, Sheu, SS, Lo, WC, Chang, SC, Hong, HC, Lo, CC, Liu, RS, Hsieh, CC, Tang, KT & Chang, MF 2024, '8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips', IEEE Transactions on Circuits and Systems I: Regular Papers, 卷 71, 編號 4, 頁 2304-2308. https://doi.org/10.1109/TCSII.2023.3331375

TY - JOUR

T1 - 8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips

AU - Su, Jian Wei

AU - Lu, Pei Jung

AU - Wu, Ping Chun

AU - Chou, Yen Chi

AU - Liu, Ta Wei

AU - Chung, Yen Lin

AU - Hung, Li Yang

AU - Ren, Jin Sheng

AU - Huang, Wei Hsing

AU - Chien, Chih Han

AU - Mei, Peng I.

AU - Li, Sih Han

AU - Sheu, Shyh Shyuan

AU - Lo, Wei Chung

AU - Chang, Shih Chieh

AU - Hong, Hao Chiao

AU - Lo, Chung Chuan

AU - Liu, Ren Shuo

AU - Hsieh, Chih Cheng

AU - Tang, Kea Tiong

AU - Chang, Meng Fan

PY - 2024/4

Y1 - 2024/4

N2 - Efforts to advance the use of analog SRAM compute-in-memory (SRAM-CIM) macros for high-precision multiply-and-accumulate (MAC) operations must deal with issues pertaining to energy efficiency, computing latency (TAC), and area overhead. This brief presents a novel SRAM-CIM structure that utilizes (1) a high input precision computing cell (HIPCC) to perform 8b-MAC operations with high multiplication throughput, and (2) a global bitline-combining (GBL-comb) scheme to improve energy efficiency by reducing the number of analog-to-digital converters (ADCs). A 28nm 384-kb SRAM-CIM macro with 20-bit output precision (near-full precision) was fabricated using a foundry-provided 28nm logic process for MAC operations with 8b-input, 8b-weight, and 16 accumulations. The resulting macro achieved a TAC of 3.6 ns with energy efficiency of 14.97 TOPS/W when applied to 8-bit MAC operations.

AB - Efforts to advance the use of analog SRAM compute-in-memory (SRAM-CIM) macros for high-precision multiply-and-accumulate (MAC) operations must deal with issues pertaining to energy efficiency, computing latency (TAC), and area overhead. This brief presents a novel SRAM-CIM structure that utilizes (1) a high input precision computing cell (HIPCC) to perform 8b-MAC operations with high multiplication throughput, and (2) a global bitline-combining (GBL-comb) scheme to improve energy efficiency by reducing the number of analog-to-digital converters (ADCs). A 28nm 384-kb SRAM-CIM macro with 20-bit output precision (near-full precision) was fabricated using a foundry-provided 28nm logic process for MAC operations with 8b-input, 8b-weight, and 16 accumulations. The resulting macro achieved a TAC of 3.6 ns with energy efficiency of 14.97 TOPS/W when applied to 8-bit MAC operations.

KW - Artificial intelligence (AI)

KW - computing-in-memory (CIM)

KW - inference

KW - local computing cell (LCC)

KW - static random-access memory (SRAM)

UR - http://www.scopus.com/inward/record.url?scp=85177057366&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2023.3331375

DO - 10.1109/TCSII.2023.3331375

M3 - Article

AN - SCOPUS:85177057366

SN - 1549-7747

VL - 71

SP - 2304

EP - 2308

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 4

ER -

8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips

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