A lossy substrate model for accurate simulation of extrinsic noise and a lossy substrate de-embedding method for precise extraction of intrinsic noise have been proven by 80 nm, super-100 GHz fT RF nMOS. The method is further applied to 65 nm 160-GHz fT nMOS to investigate aggressive gate length scaling effect on RF noise. The extrinsic noise reveals abnormally weak dependence on gate length scaling even with 50-60% improvement on f T but strong dependence on finger number. The intrinsic noise extracted through lossy substrate de-embedding can consistently reflect the gain in fT and weak dependence on finger number. The NFmin at 10 GHz can be suppressed to 0.5dB for 65 nm nMOS corresponding to an optimized drain current, which is around 0.2 dB improvement over 80 nm devices. Noise suppression due to gate length scaling becomes even more significant in higher current region. The noise reduction is attributed to lower noise resistance (Rn) and real part of optimum source admittance (Re(Y opt)). The accurate extraction of intrinsic noise provides useful guideline for RF CMOS device design and optimization in terms of speed, power, and noise.