5nm-gate nanowire FinFET

Fu Liang Yang; Di Hong Lee; Hou Yu Chen; Chang Yun Chang; Sheng Da Liu; Cheng Chuan Huang; Tang Xuan Chung; Hung Wei Chen; Chien Chao Huang; Yi Hsuan Liu; Chung Cheng Wu; Chi Chun Chen; Shih Chang Chen; Ying Tsung Chen; Ying Ho Chen; Chih Jian Chen; Bor Wen Chan; Peng Fu Hsu; Jyu Horng Shieh; Han Jan Tao; Yee Chia Yeo; Yiming Li; Jam Wem Lee; Pu Chen; Mong Song Liang; Chen-Ming Hu

doi:10.1109/VLSIT.2004.1345476

5nm-gate nanowire FinFET

Fu Liang Yang^*
, Di Hong Lee
, Hou Yu Chen
, Chang Yun Chang
, Sheng Da Liu
, Cheng Chuan Huang
, Tang Xuan Chung
, Hung Wei Chen
, Chien Chao Huang
, Yi Hsuan Liu
, Chung Cheng Wu
, Chi Chun Chen
, Shih Chang Chen
, Ying Tsung Chen
, Ying Ho Chen
, Chih Jian Chen
, Bor Wen Chan
, Peng Fu Hsu
, Jyu Horng Shieh
, Han Jan Tao

Yee Chia Yeo, Yiming Li, Jam Wem Lee, Pu Chen, Mong Song Liang, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

285 引文斯高帕斯（Scopus）

摘要

A new nanowire FinFET structure is developed for CMOS I device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage current less than 10 nA/"mu;m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

原文	English
頁（從 - 到）	196-197
頁數	2
期刊	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2004.1345476
出版狀態	Published - 2004
事件	2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, 美國持續時間: 15 6月 2004 → 17 6月 2004

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10.1109/VLSIT.2004.1345476

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Yang, F. L., Lee, D. H., Chen, H. Y., Chang, C. Y., Liu, S. D., Huang, C. C., Chung, T. X., Chen, H. W., Huang, C. C., Liu, Y. H., Wu, C. C., Chen, C. C., Chen, S. C., Chen, Y. T., Chen, Y. H., Chen, C. J., Chan, B. W., Hsu, P. F., Shieh, J. H., ... Hu, C.-M. (2004). 5nm-gate nanowire FinFET. Digest of Technical Papers - Symposium on VLSI Technology, 196-197. https://doi.org/10.1109/VLSIT.2004.1345476

@article{e470a1df04e84c4c9f50367bd1a0358d,

title = "5nm-gate nanowire FinFET",

abstract = "A new nanowire FinFET structure is developed for CMOS I device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage current less than 10 nA/{"}mu;m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.",

author = "Yang, \{Fu Liang\} and Lee, \{Di Hong\} and Chen, \{Hou Yu\} and Chang, \{Chang Yun\} and Liu, \{Sheng Da\} and Huang, \{Cheng Chuan\} and Chung, \{Tang Xuan\} and Chen, \{Hung Wei\} and Huang, \{Chien Chao\} and Liu, \{Yi Hsuan\} and Wu, \{Chung Cheng\} and Chen, \{Chi Chun\} and Chen, \{Shih Chang\} and Chen, \{Ying Tsung\} and Chen, \{Ying Ho\} and Chen, \{Chih Jian\} and Chan, \{Bor Wen\} and Hsu, \{Peng Fu\} and Shieh, \{Jyu Horng\} and Tao, \{Han Jan\} and Yeo, \{Yee Chia\} and Yiming Li and Lee, \{Jam Wem\} and Pu Chen and Liang, \{Mong Song\} and Chen-Ming Hu",

year = "2004",

doi = "10.1109/VLSIT.2004.1345476",

language = "English",

pages = "196--197",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2004 Symposium on VLSI Technology - Digest of Technical Papers ; Conference date: 15-06-2004 Through 17-06-2004",

}

Yang, FL, Lee, DH, Chen, HY, Chang, CY, Liu, SD, Huang, CC, Chung, TX, Chen, HW, Huang, CC, Liu, YH, Wu, CC, Chen, CC, Chen, SC, Chen, YT, Chen, YH, Chen, CJ, Chan, BW, Hsu, PF, Shieh, JH, Tao, HJ, Yeo, YC, Li, Y, Lee, JW, Chen, P, Liang, MS & Hu, C-M 2004, '5nm-gate nanowire FinFET', Digest of Technical Papers - Symposium on VLSI Technology, 頁 196-197. https://doi.org/10.1109/VLSIT.2004.1345476

TY - JOUR

T1 - 5nm-gate nanowire FinFET

AU - Yang, Fu Liang

AU - Lee, Di Hong

AU - Chen, Hou Yu

AU - Chang, Chang Yun

AU - Liu, Sheng Da

AU - Huang, Cheng Chuan

AU - Chung, Tang Xuan

AU - Chen, Hung Wei

AU - Huang, Chien Chao

AU - Liu, Yi Hsuan

AU - Wu, Chung Cheng

AU - Chen, Chi Chun

AU - Chen, Shih Chang

AU - Chen, Ying Tsung

AU - Chen, Ying Ho

AU - Chen, Chih Jian

AU - Chan, Bor Wen

AU - Hsu, Peng Fu

AU - Shieh, Jyu Horng

AU - Tao, Han Jan

AU - Yeo, Yee Chia

AU - Li, Yiming

AU - Lee, Jam Wem

AU - Chen, Pu

AU - Liang, Mong Song

AU - Hu, Chen-Ming

PY - 2004

Y1 - 2004

N2 - A new nanowire FinFET structure is developed for CMOS I device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage current less than 10 nA/"mu;m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

AB - A new nanowire FinFET structure is developed for CMOS I device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage current less than 10 nA/"mu;m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

UR - https://www.scopus.com/pages/publications/4544367603

U2 - 10.1109/VLSIT.2004.1345476

DO - 10.1109/VLSIT.2004.1345476

M3 - Conference article

AN - SCOPUS:4544367603

SN - 0743-1562

SP - 196

EP - 197

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2004 Symposium on VLSI Technology - Digest of Technical Papers

Y2 - 15 June 2004 through 17 June 2004

ER -

5nm-gate nanowire FinFET

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