@article{e470a1df04e84c4c9f50367bd1a0358d,
title = "5nm-gate nanowire FinFET",
abstract = "A new nanowire FinFET structure is developed for CMOS I device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage current less than 10 nA/{"}mu;m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.",
author = "Yang, {Fu Liang} and Lee, {Di Hong} and Chen, {Hou Yu} and Chang, {Chang Yun} and Liu, {Sheng Da} and Huang, {Cheng Chuan} and Chung, {Tang Xuan} and Chen, {Hung Wei} and Huang, {Chien Chao} and Liu, {Yi Hsuan} and Wu, {Chung Cheng} and Chen, {Chi Chun} and Chen, {Shih Chang} and Chen, {Ying Tsung} and Chen, {Ying Ho} and Chen, {Chih Jian} and Chan, {Bor Wen} and Hsu, {Peng Fu} and Shieh, {Jyu Horng} and Tao, {Han Jan} and Yeo, {Yee Chia} and Yiming Li and Lee, {Jam Wem} and Pu Chen and Liang, {Mong Song} and Chen-Ming Hu",
year = "2004",
doi = "10.1109/VLSIT.2004.1345476",
language = "English",
pages = "196--197",
journal = "Digest of Technical Papers - Symposium on VLSI Technology",
issn = "0743-1562",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
note = "2004 Symposium on VLSI Technology - Digest of Technical Papers ; Conference date: 15-06-2004 Through 17-06-2004",
}