5 V, 300 MSa/s, 6-bit Digital Gate Driver IC for GaN Achieving 69 % Reduction of Switching Loss and 60 % Reduction of Current Overshoot

Ryunosuke Katada*, Katsuhiro Hata, Yoshitaka Yamauchi, Ting Wei Wang, Ryuzo Morikawa, Cheng Hsuan Wu, Toru Sai, Po Hung Chen, Makoto Takamiya

*此作品的通信作者

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

A digital gate driver (DGD) is an important technology to reduce both switching loss and voltage and/or current overshoot. In this paper, a 5 V, 300 MSa/s, 6-bit DGD IC, where the gate current is varied in 64 levels for each of 16 3.3-ns time intervals, is developed using 180-nm BCD process for GaN FETs. The parameters for DGD are automatically optimized using a simulated annealing algorithm through repeated switching measurements. In the turn-on of GaN FETs at 48 V and 8 A, compared with the conventional single-step gate driving, the proposed gate drive using DGD reduces the switching loss from 3.9 μJ to 1.2 μJ by 69 % at the same the current overshoot of 3.4 A and reduces the current overshoot from 8.5 A to 3.4 A by 60 % at the same switching loss of 1.2 μJ, which clearly shows the advantage of DGD for GaN FETs.

原文English
主出版物標題2021 33rd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2021
發行者Institute of Electrical and Electronics Engineers Inc.
頁面55-58
頁數4
ISBN(電子)9784886864222
DOIs
出版狀態Published - 30 5月 2021
事件33rd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2021 - Virtual, Nagoya, Japan
持續時間: 30 5月 20213 6月 2021

出版系列

名字Proceedings of the International Symposium on Power Semiconductor Devices and ICs
2021-May
ISSN(列印)1063-6854

Conference

Conference33rd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2021
國家/地區Japan
城市Virtual, Nagoya
期間30/05/213/06/21

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