5 Gbps serial link transmitter with pre-emphasis

Chih Hsien Lin, Chung Hong Wang, Shyh-Jye Jou

研究成果: Conference contribution同行評審

15 引文 斯高帕斯(Scopus)

摘要

A high-speed serial link that achieves Gbps performance has the advantage of low cost and is thus set to become popular. In this paper, we implement the high-speed data serial link transceiver and demonstrate the pre-emphasis circuit. The overall circuit is implemented in TSMC 0.18 μm 1P6M 1.8 V CMOS process. The performance of the transceiver can reach 5 Gbps over the 10-meter long cable.

原文English
主出版物標題Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
發行者Institute of Electrical and Electronics Engineers Inc.
頁面795-800
頁數6
ISBN(電子)0780376595
DOIs
出版狀態Published - 1 1月 2003
事件Asia and South Pacific Design Automation Conference, ASP-DAC 2003 - Kitakyushu, Japan
持續時間: 21 1月 200324 1月 2003

出版系列

名字Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
2003-January

Conference

ConferenceAsia and South Pacific Design Automation Conference, ASP-DAC 2003
國家/地區Japan
城市Kitakyushu
期間21/01/0324/01/03

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