45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

Fu Liang Yang; Cheng Chuan Huang; Chien Chao Huang; Tang Xuan Chung; Hou Yu Chen; Chang Yun Chang; Hung Wei Chen; Di Hong Lee; Sheng Da Liu; Kuang Hsin Chen; Cheng Kuo Wen; Shui Ming Cheng; Chang Ta Yang; Li Wei Kung; Chiu Lien Lee; Yu Jun Chou; Fu Jye Liang; Lin Hung Shiu; Jan Wen You; King Chang Shu; Bin Chang Chang; Jaw Jung Shin; Chun Kuang Chen; Tsai Sheng Gau; Ping Wei Wang; Bor Wen Chan; Peng Fu Hsu; Jyu Horng Shieh; Samuel K.H. Fung; Carlos H. Diaz; Chii Ming M. Wu; Yee Chaung See; Bum J. Lin; Mong Song Liang; Jack Y.C. Sun; Chen-Ming Hu

doi:10.1109/VLSIT.2004.1345362

45nm node planar-SOI technology with 0.296μm² 6T-SRAM cell

Fu Liang Yang^*, Cheng Chuan Huang, Chien Chao Huang, Tang Xuan Chung, Hou Yu Chen, Chang Yun Chang, Hung Wei Chen, Di Hong Lee, Sheng Da Liu, Kuang Hsin Chen, Cheng Kuo Wen, Shui Ming Cheng, Chang Ta Yang, Li Wei Kung, Chiu Lien Lee, Yu Jun Chou, Fu Jye Liang, Lin Hung Shiu, Jan Wen You, King Chang ShuBin Chang Chang, Jaw Jung Shin, Chun Kuang Chen, Tsai Sheng Gau, Ping Wei Wang, Bor Wen Chan, Peng Fu Hsu, Jyu Horng Shieh, Samuel K.H. Fung, Carlos H. Diaz, Chii Ming M. Wu, Yee Chaung See, Bum J. Lin, Mong Song Liang, Jack Y.C. Sun, Chen-Ming Hu

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

23 引文斯高帕斯（Scopus）

摘要

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296μm². An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at IV/0.85V with excellent drive currents of 1000/740 and 530/420 μA/μm for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

原文	English
頁（從 - 到）	8-9
頁數	2
期刊	Digest of Technical Papers - Symposium on VLSI Technology
DOIs	https://doi.org/10.1109/VLSIT.2004.1345362
出版狀態	Published - 2004
事件	2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, 美國持續時間: 15 6月 2004 → 17 6月 2004

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10.1109/VLSIT.2004.1345362

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Yang, F. L., Huang, C. C., Huang, C. C., Chung, T. X., Chen, H. Y., Chang, C. Y., Chen, H. W., Lee, D. H., Liu, S. D., Chen, K. H., Wen, C. K., Cheng, S. M., Yang, C. T., Kung, L. W., Lee, C. L., Chou, Y. J., Liang, F. J., Shiu, L. H., You, J. W., ... Hu, C.-M. (2004). 45nm node planar-SOI technology with 0.296μm² 6T-SRAM cell. Digest of Technical Papers - Symposium on VLSI Technology, 8-9. https://doi.org/10.1109/VLSIT.2004.1345362

@article{c5816eb3c58a4a008c52493f23f91101,

title = "45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell",

abstract = "The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296μm2. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at IV/0.85V with excellent drive currents of 1000/740 and 530/420 μA/μm for N-FET and P-FET, respectively. The P-FET current is the best reported so far.",

author = "Yang, {Fu Liang} and Huang, {Cheng Chuan} and Huang, {Chien Chao} and Chung, {Tang Xuan} and Chen, {Hou Yu} and Chang, {Chang Yun} and Chen, {Hung Wei} and Lee, {Di Hong} and Liu, {Sheng Da} and Chen, {Kuang Hsin} and Wen, {Cheng Kuo} and Cheng, {Shui Ming} and Yang, {Chang Ta} and Kung, {Li Wei} and Lee, {Chiu Lien} and Chou, {Yu Jun} and Liang, {Fu Jye} and Shiu, {Lin Hung} and You, {Jan Wen} and Shu, {King Chang} and Chang, {Bin Chang} and Shin, {Jaw Jung} and Chen, {Chun Kuang} and Gau, {Tsai Sheng} and Wang, {Ping Wei} and Chan, {Bor Wen} and Hsu, {Peng Fu} and Shieh, {Jyu Horng} and Fung, {Samuel K.H.} and Diaz, {Carlos H.} and Wu, {Chii Ming M.} and See, {Yee Chaung} and Lin, {Bum J.} and Liang, {Mong Song} and Sun, {Jack Y.C.} and Chen-Ming Hu",

year = "2004",

doi = "10.1109/VLSIT.2004.1345362",

language = "English",

pages = "8--9",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2004 Symposium on VLSI Technology - Digest of Technical Papers ; Conference date: 15-06-2004 Through 17-06-2004",

}

Yang, FL, Huang, CC, Huang, CC, Chung, TX, Chen, HY, Chang, CY, Chen, HW, Lee, DH, Liu, SD, Chen, KH, Wen, CK, Cheng, SM, Yang, CT, Kung, LW, Lee, CL, Chou, YJ, Liang, FJ, Shiu, LH, You, JW, Shu, KC, Chang, BC, Shin, JJ, Chen, CK, Gau, TS, Wang, PW, Chan, BW, Hsu, PF, Shieh, JH, Fung, SKH, Diaz, CH, Wu, CMM, See, YC, Lin, BJ, Liang, MS, Sun, JYC & Hu, C-M 2004, '45nm node planar-SOI technology with 0.296μm² 6T-SRAM cell', Digest of Technical Papers - Symposium on VLSI Technology, 頁 8-9. https://doi.org/10.1109/VLSIT.2004.1345362

TY - JOUR

T1 - 45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

AU - Yang, Fu Liang

AU - Huang, Cheng Chuan

AU - Huang, Chien Chao

AU - Chung, Tang Xuan

AU - Chen, Hou Yu

AU - Chang, Chang Yun

AU - Chen, Hung Wei

AU - Lee, Di Hong

AU - Liu, Sheng Da

AU - Chen, Kuang Hsin

AU - Wen, Cheng Kuo

AU - Cheng, Shui Ming

AU - Yang, Chang Ta

AU - Kung, Li Wei

AU - Lee, Chiu Lien

AU - Chou, Yu Jun

AU - Liang, Fu Jye

AU - Shiu, Lin Hung

AU - You, Jan Wen

AU - Shu, King Chang

AU - Chang, Bin Chang

AU - Shin, Jaw Jung

AU - Chen, Chun Kuang

AU - Gau, Tsai Sheng

AU - Wang, Ping Wei

AU - Chan, Bor Wen

AU - Hsu, Peng Fu

AU - Shieh, Jyu Horng

AU - Fung, Samuel K.H.

AU - Diaz, Carlos H.

AU - Wu, Chii Ming M.

AU - See, Yee Chaung

AU - Lin, Bum J.

AU - Liang, Mong Song

AU - Sun, Jack Y.C.

AU - Hu, Chen-Ming

PY - 2004

Y1 - 2004

N2 - The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296μm2. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at IV/0.85V with excellent drive currents of 1000/740 and 530/420 μA/μm for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

AB - The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296μm2. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at IV/0.85V with excellent drive currents of 1000/740 and 530/420 μA/μm for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

UR - http://www.scopus.com/inward/record.url?scp=4544294969&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2004.1345362

DO - 10.1109/VLSIT.2004.1345362

M3 - Conference article

AN - SCOPUS:4544294969

SN - 0743-1562

SP - 8

EP - 9

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2004 Symposium on VLSI Technology - Digest of Technical Papers

Y2 - 15 June 2004 through 17 June 2004

ER -

45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

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45nm node planar-SOI technology with 0.296μm² 6T-SRAM cell