4/2 PAM serial link transmitter with tunable pre-emphasis

Chih Hsien Lin; Chang Hsiao Tsai; Chih Ning Chen; Shyh-Jye Jou

doi:10.1109/ISCAS.2004.1328354

4/2 PAM serial link transmitter with tunable pre-emphasis

Chih Hsien Lin^*, Chang Hsiao Tsai, Chih Ning Chen, Shyh-Jye Jou

^*此作品的通信作者

研究成果: Conference article › 同行評審

12 引文斯高帕斯（Scopus）

摘要

In this paper, we will implement a 4/2 PAM transmitter of the high-speed data serial link over cable and demonstrate a newly development of the pre-emphasis circuit. The overall circuit is implemented in TSMC 0.18um 1P6M 1.8v CMOS process. The performance of the transceiver can reach 20/10 Gbps over the 1-5 meter long cable.

原文	English
頁（從 - 到）	I952-I955
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
卷	1
DOIs	https://doi.org/10.1109/ISCAS.2004.1328354
出版狀態	Published - 2004
事件	2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, 加拿大持續時間: 23 5月 2004 → 26 5月 2004

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10.1109/ISCAS.2004.1328354

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title = "4/2 PAM serial link transmitter with tunable pre-emphasis",

abstract = "In this paper, we will implement a 4/2 PAM transmitter of the high-speed data serial link over cable and demonstrate a newly development of the pre-emphasis circuit. The overall circuit is implemented in TSMC 0.18um 1P6M 1.8v CMOS process. The performance of the transceiver can reach 20/10 Gbps over the 1-5 meter long cable.",

author = "Lin, {Chih Hsien} and Tsai, {Chang Hsiao} and Chen, {Chih Ning} and Shyh-Jye Jou",

year = "2004",

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language = "English",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "2004 IEEE International Symposium on Cirquits and Systems - Proceedings ; Conference date: 23-05-2004 Through 26-05-2004",

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AU - Lin, Chih Hsien

AU - Tsai, Chang Hsiao

AU - Chen, Chih Ning

AU - Jou, Shyh-Jye

PY - 2004

Y1 - 2004

N2 - In this paper, we will implement a 4/2 PAM transmitter of the high-speed data serial link over cable and demonstrate a newly development of the pre-emphasis circuit. The overall circuit is implemented in TSMC 0.18um 1P6M 1.8v CMOS process. The performance of the transceiver can reach 20/10 Gbps over the 1-5 meter long cable.

AB - In this paper, we will implement a 4/2 PAM transmitter of the high-speed data serial link over cable and demonstrate a newly development of the pre-emphasis circuit. The overall circuit is implemented in TSMC 0.18um 1P6M 1.8v CMOS process. The performance of the transceiver can reach 20/10 Gbps over the 1-5 meter long cable.

UR - http://www.scopus.com/inward/record.url?scp=4344672063&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2004.1328354

DO - 10.1109/ISCAS.2004.1328354

M3 - Conference article

AN - SCOPUS:4344672063

SN - 0271-4310

VL - 1

SP - I952-I955

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Cirquits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

4/2 PAM serial link transmitter with tunable pre-emphasis

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