40 nm bit-interleaving 12t subthreshold sram with data-aware write-assist

Yi Wei Chiu, Yu Hao Hu, Ming Hsien Tu, Jun Kai Zhao, Yuan Hua Chu, Shyh-Jye Jou, Ching Te Chuang

研究成果: Article同行評審

114 引文 斯高帕斯(Scopus)

摘要

This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical VDD to 350 mV (∼100 mV lower than the threshold voltage) with VDDMIN limited by Read operation. Data can be written successfully for VDD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 μW at 350 mV, 25°C.

原文English
文章編號6883245
頁(從 - 到)2578-2585
頁數8
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
61
發行號9
DOIs
出版狀態Published - 1 1月 2014

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