@inproceedings{55a3c697e70f43eb9a8d70e9a68f8a6f,
title = "3D-TCAD simulation study of the novel T-FinFET structure for sub-14nm metal-oxide-semiconductor field-effect transistor",
abstract = "We propose a novel device structure, namely T-FinFET, for sub-14nm MOSFET with using lighter anti punch through (APT) implant. According to 3D TCAD simulation, the T-FinFET is found to posses many advantages over the normal FinFET, such as better short channel effect (SCE) and drain induced barrier lowering (DIBL), having smaller S/D capacitance and junction leakage and fewer masks. Compared to gate-all-around (GAA) structure, the T-FinFET also has compatible electrical performance. All these features are obtained by depositing a self-aligned (SA) oxide after recessing the Si fin in the S/D region. It can be applied to Ge and III-V MOSFETs for suppressing the SCEs and S/D leakage, arising from higher permittivity and lower band gap than Si.",
keywords = "Doping, FinFETs, Implants, Logic gates, Process control, Solid modeling, Three-dimensional displays",
author = "Chou, {Chen Han} and Hsu, {Chung Chun} and Chung, {Steve S.} and Chien, {Chao Hsin}",
year = "2015",
month = sep,
day = "24",
language = "English",
series = "2015 Silicon Nanoelectronics Workshop, SNW 2015",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2015 Silicon Nanoelectronics Workshop, SNW 2015",
address = "United States",
note = "null ; Conference date: 14-06-2015 Through 15-06-2015",
}