3D Scalable, Wake-up Free, and Highly Reliable FRAM Technology with Stress-Engineered HfZrOx

Y. D. Lin, Y. T. Tang, S. S. Sheu, T. H. Hou, W. C. Lo, M. H. Lee, M. F. Chang, Y. C. King, C. J. Lin, H. Y. Lee, P. C. Yeh, H. Y. Yang, P. S. Yeh, C. Y. Wang, J. W. Su, S. H. Li

研究成果: Conference contribution同行評審

11 引文 斯高帕斯(Scopus)

摘要

The major challenge of FRAM scaling is to maintain high polarization density on the vertical sidewall of 3D ferroelectric capacitors. We reported a CMOS-compatible HfZrOx FRAM technology that shows a wake-up free character, 1010/109 endurance cycles, extrapolated 10-year retention at 105°C/85°C, and initial Pr = 25/18 μC/cm2 for 2D/3D FRAM, respectively. The strain effect at atomic interfaces is considered by the density functional theory (DFT) simulation. Two simple yet effective methods, stress engineering and optimized interface orientation, are proposed to facilitate preferential transition from tetragonal to orthorhombic phase. The test chip of 2T2C 3D FRAM demonstrates a fast sensing speed of 17 MHz at VDD of 4V.

原文English
主出版物標題2019 IEEE International Electron Devices Meeting, IEDM 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728140315
DOIs
出版狀態Published - 12月 2019
事件65th Annual IEEE International Electron Devices Meeting, IEDM 2019 - San Francisco, United States
持續時間: 7 12月 201911 12月 2019

出版系列

名字Technical Digest - International Electron Devices Meeting, IEDM
2019-December
ISSN(列印)0163-1918

Conference

Conference65th Annual IEEE International Electron Devices Meeting, IEDM 2019
國家/地區United States
城市San Francisco
期間7/12/1911/12/19

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