3D integration for VLSI systems

Chuan Seng Tan*, Kuan-Neng Chen, Steven Koester

*此作品的通信作者

    研究成果: Book同行評審

    17 引文 斯高帕斯(Scopus)

    摘要

    Three-dimensional (3D) integration is identified as a possible avenue for continuous performance growth in integrated circuits (IC) as the conventional scaling approach is faced with unprecedented challenges in fundamental and economic limits. Wafer level 3D IC can take several forms, and they usually include a stack of several thinned IC layers that are vertically bonded and interconnected by through silicon via TSV. There is a long string of benefits that one can derive from 3D IC implementation such as form factor, density multiplication, improved delay and power, enhanced bandwidth, and heterogeneous integration. This book presents contributions by key researchers in this field, covering motivations, technology platforms, applications, and other design issues.

    原文English
    發行者Pan Stanford Publishing Pte. Ltd.
    頁數377
    ISBN(電子)9789814303828
    ISBN(列印)9789814303811
    DOIs
    出版狀態Published - 19 4月 2016

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