3D finite-element analysis of metal nanocrystal memories variations

Jonathan T. Shaw, Tuo-Hung Hou, Hassan Raza, Edwin C. Kan

    研究成果: Conference contribution同行評審

    摘要

    We have shown the process variation effects from nanocrystal size, density, registry and gate length in 20 - 90 nm metal nanocrystal memory technology by 3D finite-element analysis. Conventional 1D analysis in the gate stack will result in severe miscalculation of bit-error-rate due to neglecting the fringing fields and percolation path in the memory cell. We also present the statistical metrology on memory windows from nanocrystal placement control and the use of nanowire devices. We conclude that the self-assembled nanocrystals in the gate stack can fit the parametric yield required for 20nm technology.

    原文English
    主出版物標題Proceedings - 2009 13th International Workshop on Computational Electronics, IWCE 2009
    DOIs
    出版狀態Published - 27 10月 2009
    事件2009 13th International Workshop on Computational Electronics, IWCE 2009 - Beijing, China
    持續時間: 27 5月 200929 5月 2009

    出版系列

    名字Proceedings - 2009 13th International Workshop on Computational Electronics, IWCE 2009

    Conference

    Conference2009 13th International Workshop on Computational Electronics, IWCE 2009
    國家/地區China
    城市Beijing
    期間27/05/0929/05/09

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