350 ps 50K 0.8 μm BiCMOS gate array with shared bipolar cell structure

Hiroyuki Hara*, Yasuhiro Sugimoto, Makoto Noda, Tetsu Nagamatsu, Yoshinori Watanabe, Hiroshi Iwai, Yoichirou Niitsu, Gen Sasaki, Kenji Maeguchi

*此作品的通信作者

研究成果: Conference article同行評審

1 引文 斯高帕斯(Scopus)

摘要

A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V.

原文English
頁(從 - 到)8.5/1-4
期刊Proceedings of the Custom Integrated Circuits Conference
出版狀態Published - 5月 1989
事件Proceedings of the IEEE 1989 Custom Integrated Circuits Conference - San Diego, CA, SA
持續時間: 15 5月 198918 5月 1989

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