350 ps 50K 0.8 μm BiCMOS gate array with shared bipolar cell structure

Hiroyuki Hara; Yasuhiro Sugimoto; Makoto Noda; Tetsu Nagamatsu; Yoshinori Watanabe; Hiroshi Iwai; Yoichirou Niitsu; Gen Sasaki; Kenji Maeguchi

350 ps 50K 0.8 μm BiCMOS gate array with shared bipolar cell structure

Hiroyuki Hara^*, Yasuhiro Sugimoto, Makoto Noda, Tetsu Nagamatsu, Yoshinori Watanabe, Hiroshi Iwai, Yoichirou Niitsu, Gen Sasaki, Kenji Maeguchi

^*此作品的通信作者

國際半導體產業學院

研究成果: Conference article › 同行評審

1 引文斯高帕斯（Scopus）

摘要

A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V.

原文	English
頁（從 - 到）	8.5/1-4
期刊	Proceedings of the Custom Integrated Circuits Conference
出版狀態	Published - 5月 1989
事件	Proceedings of the IEEE 1989 Custom Integrated Circuits Conference - San Diego, CA, SA 持續時間: 15 5月 1989 → 18 5月 1989

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@article{445892ee092942c6a56d46dbc7db8e06,

title = "350 ps 50K 0.8 μm BiCMOS gate array with shared bipolar cell structure",

abstract = "A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V.",

author = "Hiroyuki Hara and Yasuhiro Sugimoto and Makoto Noda and Tetsu Nagamatsu and Yoshinori Watanabe and Hiroshi Iwai and Yoichirou Niitsu and Gen Sasaki and Kenji Maeguchi",

year = "1989",

month = may,

language = "English",

pages = "8.5/1--4",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 15-05-1989 Through 18-05-1989",

}

TY - JOUR

T1 - 350 ps 50K 0.8 μm BiCMOS gate array with shared bipolar cell structure

AU - Hara, Hiroyuki

AU - Sugimoto, Yasuhiro

AU - Noda, Makoto

AU - Nagamatsu, Tetsu

AU - Watanabe, Yoshinori

AU - Iwai, Hiroshi

AU - Niitsu, Yoichirou

AU - Sasaki, Gen

AU - Maeguchi, Kenji

PY - 1989/5

Y1 - 1989/5

N2 - A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V.

AB - A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V.

UR - http://www.scopus.com/inward/record.url?scp=0024664435&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0024664435

SP - 8.5/1-4

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

SN - 0886-5930

Y2 - 15 May 1989 through 18 May 1989

ER -

350 ps 50K 0.8 μm BiCMOS gate array with shared bipolar cell structure

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