3-D Stacked Technology of DRAM-Logic Controller Using Through-Silicon Via (TSV)

Wen Wei Shen, Yu Min Lin, Shang Chun Chen, Hsiang Hung Chang, Tao Chih Chang, Wei Chung Lo, Chien-Chung Lin, Yung Fa Chou, Ding Ming Kwai, Ming Jer Kao, Kuan-Neng Chen*

*此作品的通信作者

研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)

摘要

This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5-μm-diameter/50-μm-length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12-μm diameter are bonded using three step temperature bonding profile. Further stacked DRAM/Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.

原文English
頁(從 - 到)396-402
頁數7
期刊IEEE Journal of the Electron Devices Society
6
發行號1
DOIs
出版狀態Published - 13 三月 2018

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