27Gbit/s AIGaAs/GaAs HBT 1:2 regenerating demultiplexer IC

K. Runge, J. L. Gimlett, R. B. Nubling, K. C. Wang, Mau-Chung Chang, R. L. Pierson, P. M. Asbeck

    研究成果: Article同行評審

    3 引文 斯高帕斯(Scopus)

    摘要

    An experimental 27 Gbit/s 1:2 regenerating demultiplexer IC based on AlGaAs/GaAs HBTs has been implemented, which features an input sensitivity of 55 mV peak to peak and a phase marpn of 270° at the SONET STS-192 rate of 9·95 Gbit/s. The circuit was fabricated in a high current gain baseline HBT technology, and occupies an area of 115 × 1 mm2.

    原文English
    頁(從 - 到)2389-2391
    頁數3
    期刊Electronics Letters
    27
    發行號25
    DOIs
    出版狀態Published - 5 12月 1991

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