摘要
A low-power low-flicker-noise receiver is demonstrated using 0.18 mu m CMOS technology. Vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are used to substitute the mixer switching core and the input stage of subsequent IF VGA. Compared with the conventional CMOS mixer, the excellent flicker noise performance is obtained. As a result, the receiver achieves a 47 dB voltage gain at 2.4-GHz, and the noise figure is 9.6 dB at IF=100 kHz and 5.6 dB for IF>300 kHz. The total current consumption is 4.3 mA at 1.8 V supply voltage.
原文 | American English |
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頁面 | 223-225 |
頁數 | 3 |
出版狀態 | Published - 20 1月 2013 |
事件 | IEEE Radio and Wireless Symposium (RWS) - Austin 持續時間: 20 1月 2013 → 23 1月 2013 |
Conference
Conference | IEEE Radio and Wireless Symposium (RWS) |
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城市 | Austin |
期間 | 20/01/13 → 23/01/13 |