2.4-GHz 7.4-mW 300-kHz Flicker-Noise-Corner Direct Conversion Receiver Using 0.18 mu m CMOS and Deep-N-Well NPN BJT

Wei-Ling Chang*, Chin-Chun Meng, Jin-Siang Syu, Chia-Ling Wang, Guo-Wei Huang

*此作品的通信作者

研究成果: Paper同行評審

摘要

A low-power low-flicker-noise receiver is demonstrated using 0.18 mu m CMOS technology. Vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are used to substitute the mixer switching core and the input stage of subsequent IF VGA. Compared with the conventional CMOS mixer, the excellent flicker noise performance is obtained. As a result, the receiver achieves a 47 dB voltage gain at 2.4-GHz, and the noise figure is 9.6 dB at IF=100 kHz and 5.6 dB for IF>300 kHz. The total current consumption is 4.3 mA at 1.8 V supply voltage.

原文American English
頁面223-225
頁數3
出版狀態Published - 20 1月 2013
事件IEEE Radio and Wireless Symposium (RWS) - Austin
持續時間: 20 1月 201323 1月 2013

Conference

ConferenceIEEE Radio and Wireless Symposium (RWS)
城市Austin
期間20/01/1323/01/13

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