TY - JOUR
T1 - 20 ns 512 kb DRAM with 83 MHz page operation.
AU - Lu, Nicky C.C.
AU - Chao, Hu
AU - Hwang, Wei
AU - Henkels, Walter
AU - Rajeevakumar, T.
AU - Hanafi, Hussein
AU - Terman, Lewis
AU - Franch, Robert
PY - 1988/12/1
Y1 - 1988/12/1
N2 - The authors describe a 128K × 4 DRAM (dynamic random-access memory) designed for high speed while retaining the traditional density advantage of the one-transistor DRAM cell. Waveforms show a row access of 20 ns, measured at 5.0 V, 25°C, and 50 pF load, and column access of 7.5 ns under the same conditions. The high-speed page mode with 12-ns cycle into 60 pF is shown. The resulting data rate is 330 MHz with a page depth of 256 b. The chip is 78 mm2 and was fabricated in a single-poly, double-metal n-well epitaxial CMOS process with an average feature size of 1.3 μm.
AB - The authors describe a 128K × 4 DRAM (dynamic random-access memory) designed for high speed while retaining the traditional density advantage of the one-transistor DRAM cell. Waveforms show a row access of 20 ns, measured at 5.0 V, 25°C, and 50 pF load, and column access of 7.5 ns under the same conditions. The high-speed page mode with 12-ns cycle into 60 pF is shown. The resulting data rate is 330 MHz with a page depth of 256 b. The chip is 78 mm2 and was fabricated in a single-poly, double-metal n-well epitaxial CMOS process with an average feature size of 1.3 μm.
UR - http://www.scopus.com/inward/record.url?scp=0024129802&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.1988.663709
DO - 10.1109/ISSCC.1988.663709
M3 - Conference article
AN - SCOPUS:0024129802
SN - 0193-6530
VL - 31
SP - 240-241, 385
JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ER -