2-V, 1.8-GHz BJT phase-locked loop

    研究成果: Article同行評審

    10 引文 斯高帕斯(Scopus)


    This paper describes the design of a bipolar junction transistor phase-locked loop (PLL) for ΣΔ fractional-N frequency-synthesis applications. Implemented in a 0.8-μm BiC-MOS technology, the PLL can operate up to 1.8 GHz while consuming 225 mW of power from a single -2-V supply. The entire LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A differential low-voltage current-mode logic circuit configuration is used in most of the PLL's functional blocks to minimize phase jitter and achieve low-voltage operation. The multimodulus frequency divider is designed to support multibit digital modulation. The new phase and frequency detector and loop filter contain only npn transistors and resistors and thus achieve excellent resolution in phase comparison. When phase locked to a 53.4-MHz reference clock, the measured phase noise of the 1.6-GHz output is -91 dBc/Hz at 10-kHz offset. The frequency switching time from 1.677 to 1.797 GHz is 150 μs. Die size is 4300 × 4000 μm2, including the passive loop filter.

    頁(從 - 到)784-789
    期刊IEEE Journal of Solid-State Circuits
    出版狀態Published - 6月 1999


    深入研究「2-V, 1.8-GHz BJT phase-locked loop」主題。共同形成了獨特的指紋。