1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation

Masud Rana Sk, Sunanda Thunder, Franz Müller, Nellie Laleni, Yannick Raffel, Maximilian Lederer, Luca Pirro, Talha Chohan, Jing Hua Hsuen, Tian Li Wu*, Konrad Seidel, Thomas Kämpfe, Sourav De*, Bhaswar Chakrabarti*

*此作品的通信作者

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current (Id) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current (IBL) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.

原文English
頁(從 - 到)424-429
頁數6
期刊IEEE Transactions on Nanotechnology
22
DOIs
出版狀態Published - 2023

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