TY - GEN
T1 - 15MHz wide tuning-range OTA with 69dBHD3 and its application to Gm-C filter
AU - Lin, Jun Ye
AU - Chang, Wei Hsiu
AU - Hung, Chung-Chih
PY - 2011/6/28
Y1 - 2011/6/28
N2 - This paper presents a high linearity operational transconductance amplifier (OTA). The OTA circuit combines the techniques of the double differential pairs (DDP) and Source-degenerated current mirrors to achieve high linearity in a large GM tuning range. With the Gm values ranged from 60μS to 130μS, the HD3 of the OTA is below 69dB at 15MHz. The OTA has been applied to a fourth-order linear phase low-pass filter for high speed system. The fourth-order low-pass filter with the cutoff frequency of 15MHz has been implemented. The filter is designed by 0.18-μm CMOS process technology, the HD3 performance is about 53dB, and the group delay variation is below 5% at cutoff frequency.
AB - This paper presents a high linearity operational transconductance amplifier (OTA). The OTA circuit combines the techniques of the double differential pairs (DDP) and Source-degenerated current mirrors to achieve high linearity in a large GM tuning range. With the Gm values ranged from 60μS to 130μS, the HD3 of the OTA is below 69dB at 15MHz. The OTA has been applied to a fourth-order linear phase low-pass filter for high speed system. The fourth-order low-pass filter with the cutoff frequency of 15MHz has been implemented. The filter is designed by 0.18-μm CMOS process technology, the HD3 performance is about 53dB, and the group delay variation is below 5% at cutoff frequency.
UR - http://www.scopus.com/inward/record.url?scp=79959522020&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2011.5783589
DO - 10.1109/VDAT.2011.5783589
M3 - Conference contribution
AN - SCOPUS:79959522020
SN - 9781424484997
T3 - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
SP - 108
EP - 111
BT - Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
T2 - 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Y2 - 25 April 2011 through 28 April 2011
ER -