1.2 kV 4H-SiC VDMOSFETs with Si-implanted Surface: Performance Enhancement and Reliability Evaluation

J. W. Hu, J. Y. Jiang, P. W. Huang, C. F. Huang, S. W. Tang, Z. H. Huang, Tian-Li Wu, K. Y. Lee

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper reports on the performance improvement in 1.2KV 4H-SiC VDMOSFETs using a Si-implanted surface technique. Firstly, the devices with Si implantation on the surface shows a decrease of carbon atom percentage from XPS and EDX analysis, an improvement of subthreshold slope (SS) and mobility in n-MOSFETs, and a lower interface state density (DIT) near the conduction band edge from n-MOS capacitors. Secondly, high-voltage VDMOSFETs with Si implantation on the surface shows an improvement in SS, ID, breakdown voltage, and electrical safe operating area (SOA). Finally, the reliability including positive/negative bias temperature instability (PBTI/NBTI) and RON stability under high-voltage pulses are evaluated in high-voltage VDMOSFETs. Therefore, the Si-implanted surface technique is effective in enhancing the performance of 4H-SiC power VDMOSFETs without stability concerns.

原文English
主出版物標題2021 33rd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2021
發行者Institute of Electrical and Electronics Engineers Inc.
頁面211-214
頁數4
ISBN(電子)9784886864222
DOIs
出版狀態Published - 30 5月 2021
事件33rd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2021 - Virtual, Nagoya, Japan
持續時間: 30 5月 20213 6月 2021

出版系列

名字Proceedings of the International Symposium on Power Semiconductor Devices and ICs
2021-May
ISSN(列印)1063-6854

Conference

Conference33rd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2021
國家/地區Japan
城市Virtual, Nagoya
期間30/05/213/06/21

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