1.2μm Bi-CMOS technology with high performance ECL

H. Iwai*, Y. Niitsu, G. Sasaki, M. Norishima, K. Shino, Y. Unno, K. Tsugaru, H. Hara, Y. Sugimoto, K. Kanzaki

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

1.2μm Bi-CMOS technology with ECL gate for high speed device has been developed. A process is carefully optimized for obtaining the best performance of ECL gate without degrading 1.2μm Bi-CMOS performance and mass productivity.

原文English
主出版物標題ESSDERC 1987 - 17th European Solid State Device Research Conference
發行者IEEE Computer Society
頁面29-32
頁數4
ISBN(電子)0444704779
ISBN(列印)9780444704771
出版狀態Published - 1987
事件17th European Solid State Device Research Conference, ESSDERC 1987 - Bologna, Italy
持續時間: 14 9月 198717 9月 1987

出版系列

名字European Solid-State Device Research Conference
ISSN(列印)1930-8876

Conference

Conference17th European Solid State Device Research Conference, ESSDERC 1987
國家/地區Italy
城市Bologna
期間14/09/8717/09/87

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